For more information about this programme, please contact: [email protected]

FlexiMasters in Integrated Circuit Design

This FlexiMasters programme is conceived and developed by Nanyang Technological University (NTU) and fabless semiconductor companies in Singapore in collaboration with the Singapore Semiconductor Industry Association (SSIA) to train and develop more integrated circuit (IC) design talent with industry-ready skill sets.

The FlexiMasters aims to provide graduates, practising engineers, R&D managers and technical staff technical knowledge as well as practical hands-on experience in the area of digital IC design. Digital IC design is an important foundation for professionals to create cutting-edge semiconductor innovations and power the next generation of smart, high-performance technologies.

The FlexiMasters in Integrated Circuit Design is mapped to the Master of Science (MSc) in Integrated Circuits and Microelectronics from NTU School of Electrical and Electronic Engineering (EEE).

Singapore to launch new training programme to boost semiconductor talent pool: Gan Kim Yong, Deputy Prime Minister of Singapore

Semiconductors are the backbone of today's fast-growing economy, contributing more than one-third of Singapore's overall manufacturing value-add. With the accelerating adoption of AI, 5G and the industrial Internet of Things, the global semiconductor industry is on track to surpass the trillion-dollar mark by 2030.

Master In-Demand IC Design Skills: Provides both basic modules as well as advanced modules so that learners will receive practical training and understand the challenging demands of IC design industry.

Industry-Relevant: Courses are designed in collaboration with industry partners to meet the specific skills needed in the semiconductor industry.

Practical Curriculum: Aims to bridge the gap between theoretical digital IC design concepts and real-world implementations, through hands-on lab training using industry-standard electronic design automation (EDA) tools, including Verilog code, full-custom library cell design, and Graphic Data Systems II (GDSII) generation.

Boost Career Prospects: Equip yourself with practical skills to become a competitive candidate for roles in both domestic and international markets.

The programme consists of 8 courses, each of which is 3 Academic Units (AUs).
Mode of class delivery: Classroom learning
Assessments will be conducted during every course and learners will be graded based on their performance in the assessments.
Shortlisting will be conducted for this programme.

Bridging Courses

FlexiMasters Courses (Basic)

FlexiMasters Courses (Advanced)

Digital IC Design Theory

Digital IC Design with CAD

Digital IC Frontend Design

Digital IC Backend Design

Digital IC Design for Testability

Digital Integrated Circuit Design

Computer Architecture

FPGA Prototyping

IC Verification Theory

IC Verification Lab

Graduate Certificate

Complete any 3 Courses (Basic or Advanced) with minimum Grade Point > 2.5

FlexiMasters

Complete any 5 Courses (Basic or Advanced) with minimum Grade Point > 2.5

Upon successful completion, the following qualifications will be awarded:

A Graduate Certificate will be awarded to learners attaining 9 AUs, with a minimum Grade Point of 2.5 (which is equivalent to a letter grade of C+) achieved for each course.
A FlexiMasters will be awarded to learners attaining 15 AUs and achieve a minimum Grade Point of 2.5 (which is equivalent to a letter grade of C+) in each course.

Pathway to the Master's programme: The minimum Grade Point eligible for transfer of credits to the MSc in Integrated Circuits and Microelectronics is 2.5 (which is equivalent to a letter grade of C+). Credits earned are valid for 5 years for transfer of credits to the MSc in Integrated Circuits and Microelectronics. Please note that only up to 15 AUs can be transferred to the MSc in Integrated Circuits and Microelectronics. Transfer of credits is by application, and the application will be assessed and approved by the University in accordance with University Credits Transfer and Course Exemption Policy.

Assessments are conducted during every course. These may include class participation, individual or group assignments, project presentations, quizzes and/or written examinations, depending on the course.

Recent graduates in electrical engineering, electronics or related engineering disciplines
Practising engineers and R&D managers in the IC / semiconductor sector
Technical staff seeking structured upskilling in digital IC design

Admission criteria:

No pre-requisites are needed to enrol in the individual courses.
A formal bachelor's degree is a pre-requisite for the FlexiMasters and Master's pathways.
Relevant engineering background or work experience (up to 2 years) is advantageous. Learners without qualifications or working experience in relevant engineering or related fields may find the course contents challenging.
Shortlisting will be conducted.

Language competency:

For applicants whose native language is not English, TOEFL/IELTS score would be required to be submitted during the application. Test dates must be within 2 years or less from the date of application.
Applicants without TOEFL/IELTS may be subjected to an interview/test.

Career prospects:

Digital IC Design Engineer (Frontend)
EDA/Design Automation Engineer
Physical Design/Implementation Engineer (Backend)
Verification Engineer
Roles in system-on-chip (SoC) integration & validation

Course Title

Objectives

Digital IC Frontend Design

(Basic)

This course aims to bridge the gap between theoretical digital IC design concepts and real-world implementations, through hands-on lab training on front-end design of digital ICs. The lab sessions will cover a wide range of digital IC front-end design skills with EDA tools including Verilog code, Behaviour and RTL designs and simulations, logic and circuit synthesis, timing analysis, formal verification, netlist generation, design optimisations and debugging. After completion of this course, learners should be able to apply digital IC front-end design principles into practical implementation using Synopsys EDA tools and understand the integration of design methodologies within the broader VLSI design flow.

As this micro-credential course is only offered in the FlexiMasters in Integrated Circuit Design programme, learners are required to enrol into the programme and complete all required courses within this programme.

At the end of the course, learners will be able to:

Design and characterise basic CMOS cells
Implement sequential and combinational digital circuits with Hardware Description Language (HDL)
Construct testbenches for simulation and design validation
Perform logic synthesis with technology mapping
Simulate corner conditions for design optimisation

Digital IC Backend Design

(Basic)

This course aims to bridge the gap between theoretical digital IC design concepts and real-world implementations, through hands-on lab training on back-end design of digital ICs. This course will cover a wide range of digital IC back-end design skills with EDA tools including full-custom library cell design, floor planning, power planning, placement, clock tree synthesis, routing, timing analysis, design rule checking, layout and stick diagram, routing, layout versus schematic verification, pre- and post-layout power and delay simulations, critical path analysis and GDSII generation. After completion of this course, learners should be able to apply digital IC back-end design principles into practical implementation using Cadence EDA tools, and demonstrate proficiency in manual and automatic layout, routing, and physical verification.

At the end of the course, learners will be able to:

Integrate back-end design methodologies within the broader VLSI design flow, from synthesis to GDSII
Demonstrate proficiency in layout, routing, and physical verification using industry-standard EDA tools
Apply digital IC back-end design principles into practical implementation, focusing on power, area, and timing optimisation
Analyse and verify digital designs through timing analysis, Design Rule Checking (DRC), and Layout Versus Schematic (LVS) verification

Digital IC Design for Testability

(Basic)

This course provides an introduction to digital IC design for testability, equipping learners with the essential knowledge and skills to design digital circuits after considering testing. It covers a wide range of concepts, including basic VLSI testing, device failure mechanisms, testing techniques, design for test, built-in-self-test, memory testing, and IEEE test standards. By bridging the gap between digital IC design theory and practical circuit design in industry, this course prepares learners to meet the industry-level standards in testing.

At the end of the course, learners will be able to:

Explain the concepts and principles of VLSI testing
Explain IC device failure mechanisms and accelerated testing
Explain IC fault models
Explain the concept of testability
Identify key techniques for test vector generation
Identify key techniques for fault simulation
Compare functional testing with current-based testing
Explain design for testability (DFT)
Explain built-in-self-test (BIST)
Explain random access memory test
Explain basic IEEE standards for testing

Digital Integrated Circuit Design

(Advanced)

This course provides a comprehensive introduction to Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and its second-order transistors’ effects. Silicon devices processes, CMOS process enhancements, and layout design rules will all be discussed. The working principle of CMOS logic circuits (both static and dynamic), consideration for power, understanding of the issues of low voltage and low power, as well as the sensitivity analyses of CMOS digital circuits will be discussed. Bipolar Complementary Metal-Oxide-Semiconductor (BiCMOS) devices used in niche areas of digital IC design is also described. The last part of the course covers the design methodologies, concepts on design flow, design analysis, verification, different implementation approaches, design synthesis and test methods.

The topics taught provide learners important background knowledge to present-day devices and circuit designs, providing a strong foundation for the learning of future newly developed semiconductor devices, circuits and their applications.

At the end of the course, learners will be able to:

Explain the principles of transistor device physics and describe secondary effects of these devices
Describe the basic silicon devices processes and apply CMOS design rules to draw a layout for a block of CMOS circuits
Analyse and design digital CMOS circuits with high speed and more importantly, low power considerations
Describe the BiCMOS processes and able to analyse and design BiCMOS digital circuits
Explain digital functional modules and more complex digital integrated systems with low power consumption

Computer Architecture

(Advanced)

This course equips learners with the essential concepts and principles in computer architecture so that they have in-depth understanding of computer system organisations and computer system designs. This includes machine models and the components of a modern Central Processing Unit (CPU), including the Arithmetic Logic Unit (ALU) and registers, from the transistor-level to the combinatorial circuits and memory units. Learners will also learn about the design of simple instruction set architectures, including Million Instructions Per Seconds (MIPS), and how a CPU communicates via buses with Input/Output (I/O) devices, and the basics of memory caches as well as how CPU pipelining is done. This course also enables learners to quantitatively analyse, compare, and evaluate the performance of computer systems.

At the end of the course, learners will be able to:

Explain the concepts and principles of computer design, including machine models and the concept of stored-program computers
Describe the components of a modern CPU, including the ALU and registers, from the transistor-level to combinatorial circuits and memory units
Explain the design of simple instruction set architectures, including MIPS
Describe how a CPU communicates via buses with I/O devices
Compare performance of computers and storage devices in various dimensions
Deduce the method of improving CPU performance through a cache memory with the use of temporal and spatial locality
Describe the five steps of a Deluxe (DLX) machine operating on un-pipelined hardware and explain the DLX main features such as fixed instruction format, fixed instruction length, Load/Store architecture, different addressing modes and the use of numerous registers
Differentiate the structural, data and control hazards associated with pipelined DLX execution and be able to devise methods to remove or reduce these hazards

Venue: NTU Main Campus

Course Title	Class Schedule	Frequency & Timing	Registration Closing Date

Digital IC Frontend Design	17 Jun - 3 Jul 2026 Apply here	Daily 9.30am - 12.30pm	20 May 2026
Digital IC Backend Design	22 Jun - 8 Jul 2026 Apply here	Daily 2pm - 5pm	25 May 2026
Digital IC Design for Testability	AY26/27 Sem 1 (Aug - Dec 2026)	Once a week 6.30pm - 9.30pm	TBD
Digital Integrated Circuit Design
Computer Architecture
IC Verification Theory	AY26/27 Sem 2 (Jan - May 2027)
IC Verification Lab
FPGA Prototyping		Once a week Timing TBD

Listed courses are:

Credit-bearing and stackable to Graduate Certificate in Integrated Circuit Design (9 AU), FlexiMasters in Integrated Circuit Design (15 AU) and MSc in Integrated Circuits and Microelectronics (30 AU).

Note:

Part-time learners are advised to register for up to a maximum of 3 courses each semester.
To facilitate the shortlisting process, please submit your highest qualification certificate(s) and transcript(s) at the point of course registration(s).
NTU reserves the right to change the date, venue, and mode of delivery due to unforeseen circumstances.

These courses are part of:

Graduate Certificate in Integrated Circuit Design (9 AU)
FlexiMasters in Integrated Circuit Design (15 AU)
MSc in Integrated Circuits and Microelectronics (30 AU)

Learners will receive their Statement of Accomplishment (for a grade of D and above) or Certificate of Participation for each course - dependent upon their assessment performance.

Programme Fee: S$28,078.40 (inclusive of GST)

Funding Support	BEFORE funding & GST		AFTER funding & 9% GST
Funding Support	Programme Fee	Course Fee	Programme Fee Payable	Course Fee Payable
Singapore Citizen (SC) and Permanent Resident (PR) (70% funding)	S$25,760	S$5,152	S$8,423.52	S$1684.70

Note:

NTU/NIE alumni may utilise their Alumni Course Credits. Click here for more information.

Prof Cheng Tee Hiang Instructor for: Computer Architecture	Dr. Cheng Tee Hiang received his BEng and PhD in Electrical and Electronic Engineering from the University of Strathclyde (1988, 1992). He is a Professor at NTU, where he has held academic leadership roles including Director of the Network Technology Research Centre, Head of the Communication Engineering Division, Associate Chair (Faculty), and Acting Chair. His expertise is in computer communication and networking, and he has taught a wide range of information technology courses at both undergraduate and graduate levels over more than 30 years in academia.
Assoc Prof Goh Wang Ling Instructor for: Digital Integrated Circuit Design	Dr. Goh Wang Ling received both her Bachelor of Engineering Degree in Electrical and Electronic Engineering and Doctor of Philosophy in Microelectronics from the Department of Electrical and Electronic Engineering at the Queen’s University of Belfast in United Kingdom. Dr. Goh is an Associate Professor at the NTU School of EEE. She is a member of the NTU Teaching Council and a Co-Chair of the NTU Teaching Excellence Academy Executive Committee. She is also Deputy Programme Director of the MSc (Electronics) Programme. Dr Goh will assume the role of Associate Vice Provost (Student Engagement & Vibrancy) in January 2026. Her previous academic roles include Associate Dean (Academic) at the Graduate College, Deputy Director (Undergraduate) of the Renaissance Engineering Programme, Associate Dean (Outreach & External Relations) at the College of Engineering, B.Eng (EEE) Full-Time Programme Coordinator, and Assistant Chair of Students at School of EEE and Assistant Head of Division at School of EEE. Dr. Goh’s research interests include digital/mixed-signal Integrated Circuit, as well as biomedical and neuromorphic circuits.
Assoc Prof Gwee Bah Hwee Instructor for: Digital IC Frontend Design Digital IC Backend Design Digital Integrated Circuit Design	Dr. Gwee Bah Hwee received his B.Eng degree from University of Aberdeen, UK, in 1990. He received his MEng and PhD degrees from NTU in 1992 and 1998 respectively. He was an Assistant Professor of School of NTU EEE from 1999 to 2005. He is currently an Associate Professor cum Associate Chair (Students) in NTU School of EEE, and concurrently, he is the Director of National Integrated Centre for Evaluation (NiCE). He has worked on a number of research projects with research grant amounting to S$15m, including the principal investigator of the research projects from Ministry of Education (MOE) Tier-2 grant of S$1.3m, ASEAN-EU University Network Programme grant of €200k, Defence Science Organisation grant of S$6m, National Research Foundation grant of S$2.3m and A*STAR grant of S$1.1m. His research interests include machine learning, hardware security, image processing, asynchronous circuit design, Class-D amplifiers, digital signal processing. He has published more than 150 technical papers and 5 granted US patents. He has started 2 start-up companies in 2005 and in 2020.
Assoc Prof Jong Ching Chuen Instructor for: Digital Integrated Circuit Design	Dr. Jong Ching Chuen obtained his BSc (Eng) and PhD in Electronic Engineering from Queen Mary, University of London, UK. He had worked in the area of high-level synthesis of digital systems for more than 3 years both in the academics and the industries in UK before he joined NTU as a faculty member. He is now an Associate Professor in the NTU School of EEE. Dr. Jong is a Chartered Engineer (CEng), a Chartered IT Professional (CITP) and a member of the British Computer Society (BCS). His current technical interest includes arithmetic circuits, VLSI architectures, digital IC design and fast-prototyping of digital systems with FPGA.
Assoc Prof Kim Tae Hyoung Instructor for: Digital IC Design for Testability	Dr. Kim Tae Hyoung received the B.S. and M.S. degrees in electrical engineering from Korea University, Seoul, Korea. He received the Ph.D. degree in electrical and computer engineering from the University of Minnesota, Minneapolis, MN, USA in 2009. From 2001 to 2005, he worked for Samsung Electronics where he performed research on the design of high-speed SRAM memories, clock generators, and IO interface circuits. In 2007-2009 summer, he was with IBM T. J. Watson Research Center and Broadcom Corporation where he performed research on isolated NBTI/PBTI measurement circuits and SRAM Mismatch measurement test structure, and battery-backed memory design, respectively. In November 2009, he joined NTU where he is currently an associate professor. His current research interests include in-memory computing for edge computing, emerging memory circuit design, energy-efficient circuits and systems for IoT and wearable devices, variation and aging tolerant circuits and systems, and circuit techniques for 3-D ICs.
Assoc Prof Lim Meng-Hiot Instructor for: Digital IC Frontend Design Digital IC Backend Design	Dr. Meng-Hiot Lim is a faculty in the School of EEE. He was one of the founding co-directors of the M.Sc. in Financial Engineering and the Centre for Financial Engineering, anchored by the Nanyang Business School. A versatile researcher with diverse interests, his areas of research focus include computational intelligence, machine learning, AI hardware, finance, algorithms for UAVs and memetic computing, and more recently in pedagogical engineering. He was the founding Editor-in-Chief of Memetic Computing Journal by Springer, and currently he serves as the Technical Editor-in-Chief. He is the Chief Editor of Proceedings on Adaptation, Learning and Optimization (PALO) series and is also a Book Series Editor of Smart Systems Technology by Springer. He has significant experience in industrial funded projects with companies such as Seiko, ST Engineering, Boeing USA and others. Being a key initiator and founding director of Garage@EEE, he helped to promote and nurture student start-ups. He is also a founder and advisor of EEE ViPod club and NTU Uavionics club.
Dr Cheng Deruo Instructor for: Digital IC Frontend Design Digital IC Backend Design	Dr. Cheng Deruo received his B.Eng degree with First Class Honours from NTU in 2016 under the full scholarship from Singapore MOE, and he received his PhD degree from NTU in 2021 under NTU Research Scholarship. He is currently a Research Scientist with Temasek Laboratories at NTU (TL@NTU), and the co-PI of S$500k research grant from Defence Science Organisation, Singapore. He has been awarded with the Research Quality Award from TL@NTU consecutively in 2023-2025. Dr. Cheng is a member of IEEE CASS DSP Technical Committee and a member of IEEE CASS Singapore Chapter Committee. His research interests include IC design, hardware security, digital forensics, image processing, multi-modal imaging, and machine learning.
Dr Nguyen Hong Duc Instructor for: Computer Architecture	Dr. Nguyen Hong Duc received his BEng and PhD in EEE from NTU (2020, 2025). He is currently a Research Fellow at NTU. His expertise is in computer vision and deep learning, and he has taught different information technology courses at NTU.

FlexiMasters in Integrated Circuit Design

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