Centre of Hardware Assurance


The vision of Centre of Hardware Assurance (CHA) is to be the National Centre of Excellence for Hardware Assurance.

The mission of CHA is to provide analysis capability from non-invasive to invasive techniques in vulnerability assessment, forensics and certification of hardware devices and components. CHA comprises three main research groups, the Hardware Analysis team (HA), Circuit Analysis (CA) team and Physical Analysis & Cryptographic Engineering (PACE) team. The HA team focuses on developing new techniques using state-of-the-art failure analysis tools for package and chip access, imaging and security assessment. The CA team researches on the design and development of advanced algorithms and tools for automatic and efficient analysis of VLSI digital integrated circuits, utilizing deep learning techniques for better adaptability and productivity. PACE team aims to advance side-channel and fault analysis techniques for hardware security analysis.

CHA collaborates with various international partners from the academia and industry, as well as local partners from the DSO National Lab, Cybersecurity Agency (CSA) and Ministry of Home Affairs (MHA).​​​​​​​​​​​​

The cryptography research team explores a range of topics such as symmetric-key cryptography, with a special focus on hash functions, block ciphers and cryptanalysis. The team also researches in lightweight cryptography, aimed for very constrained environments, and designing ne​w primitives. Recently, the team started to explore how machine learning can potentially be a help for the cryptanalysts.

Prof Thomas is the co-designer GIFT and SKINNY, currently some of the smallest known symmetric-key cryptography primitives. He also co-designed the Deoxys-II algorithm for authenticated encryption, which was selected in 2019 as winner for the CAESAR competition for authenticated encryption primitives: https://competitions.cr.yp.to/caesar-submissions.html

He is also part of the team that computed the very first collision for the secure hash algorithm (SHA-1) compression function: https://sites.google.com/site/itstheshappening/
Physical Analysis & Cryptography Engineering (PACE) team was established to lay foundations of research on hardware security. Over the years, PACE has emerged as a leading laboratory conducting cutting-edge research by developing strong capabilities in non-invasive to semi-invasive security evaluation methods. The focus is on all aspects of cryptographic engineering, and in particular on side-channel and fault analysis. The developed equipment facility and collaboration with leading research groups worldwide allows PACE team to constantly improve its knowledge and capabilities. ​​​
The Circuit Analysis team focuses on research, design and development of advanced algorithms and tools for automatic and efficient analysis of very-large-scale integration (VLSI) digital integrated circuits and systems implemented in ASICs/ FPGAs in order to understand the functionality thereof and de​tect potential malicious alteration if any. The analysis is carried out at various layers of the VLSI circuits, including register-transfer level (RTL), logic, layout and physical, to ensure complete coverage for hardware security. Contemporary Artificial Intelligence, particularly Deep Learning techniques are extensively employed in the analysis methodologies for better adaptability and productivity. Other relevant research areas include image processing, parallel computation, graph theory and graph analysis, signal and time series analysis, optimization algorithms and formal verification