Co-Founder and Security Expert

NinjaLab

France

Abstract:

In this talk we will present our public research works about practical side-channel attacks on real world devices. We will describe how we studied the side-channel security of secure devices like the Ledger Nano S (the most sold crypto-currency wallet), the Google Titan Security Key (the hardware token for second factor authentication used by all Google employees) and the Yubico Yubikey Series 5 (the most sold hardware token for second factor authentication with 40% of market share), found a vulnerability, and transformed it in a practical key-recovery attack.

Biography:

Institute Chair Professor

Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur

India

Abstract:

In today’s connected world of billions of devices, securing critical and personal data is vital, requiring solutions that address both cryptographic methods and their practical implementations. Meanwhile, advances in machine learning (ML) and deep learning (DL) present both opportunities and challenges for security.

This talk highlights how ML/DL can mount powerful attacks on cryptographic implementations via side-channel analysis and fault evaluation, while also aiding in hardness assessment—the foundation of cryptography. Conversely, cryptography and side-channel techniques can improve ML robustness by addressing timing leakages in libraries that risk input privacy. We also examine the limitations of Trusted Architectures and explore cryptographic methods for privacy-preserving machine learning (PPML).

Finally, we present SEC (Symmetric Encrypted Computation), a scalable framework for PPML, emphasizing the deep interconnection between security and ML.

Biography:

Dr. Debdeep Mukhopadhyay is an Institute Chair Professor in the Department of CSE at IIT Kharagpur, where he founded the Secured Embedded Architecture Laboratory (SEAL) focusing on hardware security. He previously held positions at NYU Abu Dhabi, NTU Singapore, NYU Shanghai, Brooklyn, IIT Madras, and IIT Bhubaneswar. He holds a Ph.D., M.S., and B.Tech from IIT Kharagpur. 

His research spans cryptographic engineering, micro-architectural security, hardware security, dependable AI, adversarial ML, and encrypted computations, including homomorphic encryption and privacy-preserving ML. He has published over 300 papers, serves on leading editorial boards, and is Editor-in-Chief of IACR TCHES (2025) and Senior Editor of IEEE TIFS.

A recipient of the Shanti Swarup Bhatnagar Award (2021), Dr. Mukhopadhyay is a Fellow of IEEE, FNA, FASc, FNAE, and FAAIA. His recognitions include the Qualcomm Faculty Award (2022), Khosla Award (2021), DST Swarnajayanti Fellowship, and inclusion among Asia’s most outstanding researchers by Asian Scientist Magazine.

Professor

Embedded Systems Security at FI CODE, University of the Bundeswehr Munich

Germany

Cryptography Consultant

PQShield

United Kingdom

Abstract:

In this talk, we explore current trends in HW acceleration and the security challenges of PQC, focusing on the design of high-performance cryptographic engines. We present a scalable and efficient hardware architecture tailored for accelerating ML-KEM and ML-DSA as an example, emphasizing both throughput and SCA resistance. A central theme is crypto agility: how to design hardware that is not only efficient and secure, but also flexible enough to support evolving PQC standards. We then focus on a key bottleneck in secure implementations: mask conversion between Boolean and arithmetic domains (B2A/A2B), which is critical for masked polynomial operations in ML-KEM and ML-DSA. To address this, we introduce a novel, constant-time single-cycle B2A conversion algorithm designed for hardware, enabling fast and secure integration of masking countermeasures. This talk combines architectural insight with practical cryptographic engineering to support the next generation of secure PQC hardware designs.

Biography:

Michael Hutter is professor for Embedded Systems Security at the Research Institute CODE, University of the Bundeswehr Munich, Germany. He has over 20 years of experience in secure hardware design and currently serves as a cryptography consultant at PQShield, a cybersecurity spin-off from the University of Oxford, UK. Formerly he was working as a Senior Principal Engineer at Rambus Cryptography Research Division (CRI), USA. He received a Venia Docendi (Habilitation) in 2016 and a PhD in Hardware Security in 2014 from Graz University of Technology, Austria. He has (co-)authored 60+ conference and journal publications in cryptography and IT security and is co-inventor of 20+ internationally pending or granted patents.

Professor

Faculty of Design Computer Science Media, RheinMain University of Applied Sciences

Germany

Abstract:

The migration of cryptographic algorithms is an emerging topic in the context of the transition to post-quantum algorithms. Various transition strategies have been proposed at both governmental and academic levels. However, these proposals primarily focus on the administrative level and abstractly call for crucial steps such as cryptographic evaluation and prioritization of algorithms for full system transition. Nevertheless, there is a lack of fundamental methods for prioritizing the migration of cryptographic algorithms. Furthermore, a clear and structured approach to identifying the dependencies of algorithmic and cryptographic assets that significantly impact the migration and system is not yet sufficiently researched. In this talk, we will present initial steps towards a structured approach based on a key-centric method to prioritize the exchange of cryptographic algorithms and related cryptographic assets for a managed migration process.

Biography:

Professor

Computer Security and Industrial Cryptography (COSIC), Department of Electrical Engineering, KU Leuven

Belgium

Abstract:

Post-quantum cryptography (PQC) is a new class of cryptography that resists in theory (mathematical) attacks from quantum computers. Indeed, PQC relies on new mathematical foundations for which no efficient quantum algorithms have been discovered yet to break them. PQC is at the basis of new standardization efforts for public key cryptography and digital signatures. Its lattice-based mathematical structures are also the foundation for fully homomorphic encryption schemes, and computing on encrypted data in general. This seminar will focus on the digital design challenges of these novel cryptographic structures on existing hardware platforms: CPU, GPU, FPGA, ASIC. On top, these implementations also must resist a wide variety of side-channel, fault, and micro-architectural attacks or any combination of them. In this presentation, we will demonstrate up to date attacks and research results to address these challenges.

Biography:

Embedded security expert

Agence nationale de la sécurité des systèmes d'information (ANSSI)

France

Abstract:

Side-channel attacks following a classical differential power analysis (DPA) style are well understood, along with the effect the masking countermeasure has on them. However, simple attacks (SPA) where the target variable does not vary thanks to a known value, such as the plaintext, are less studied. In this presentation, we show how the masking countermeasure affects the success rate of simple attacks. To this end, we provide theoretical, simulated, and practical experiments. Interestingly, we show that masking can allow to asymptotically recover more information on the secret than in the case of an unprotected implementation, depending on the masking type. In particular, this holds for masking encodings that add non-linearity with respect to the leakages, such as arithmetic masking, while it is not for Boolean masking. We also show practical implications in the context of post quantum cryptography. 

Biography:

Romain Poussier works at the French National security agency (ANSSI), in one of the research laboratories. His main topics of interest are cryptography, embedded security and side-channel attacks. Prior to this position, he did his PhD at the Université Catholique de Louvain in Belgium, and a post-doctoral research position at Nanyang Technological University in Singapore.

Senior researcher

Cyber Physical Security Research Institute, National Institute of Advanced Industrial Science and Technology (AIST)

Japan

 Abstract:

In supply chain, manufacturing of the integrated circuit (IC) is followed by "software injection/loading," which is the process of installing software onto devices during manufacturing and production of devices. In this talk, we will focus on cybersecurity threats at software injection process and consider security requirements of IC chips required to mitigate these risks. Based on this consideration, we will develop a document on security requirements specification (SRS) of secure software injection for IC chips with the important objective that this document is validated by a consortium with the third parties consisting of stakeholders of devices. Our target consortium is a forum called ICSS-UF (ICSS User Forum) which ICSS-RT (IC System Security -Round Table) has just launched in it. ICSS-RT is a Japanese consortium for establishing a framework for evaluating the security of ICs and their Systems in Japan. We expect that our SRS will be discussed and validated in ICSS-UF. We believe that the above contribution will help small-mid enterprises within a supply chain, which manufacture devices or their parts but do not invest much in security measures at production site.

Biography:

Dr Kota Ideguchi is a senior researcher in the Security Assurance Scheme Research Group, Cyber Physical Security Research Institute, National Institute of Advanced Industrial Science and Technology (AIST). He received his B.S., M.S., and Ph.D. degrees in science from the University of Tokyo. He specializes in IoT security and symmetric cryptography.

Assistant Professor

Advanced Technology Development Centre, Indian Institute of Technology Kharagpur (IIT Kharagpur)

India

 Abstract:

Homomorphic Encryption enables ML frameworks to compute directly on encrypted data. The main challenge to design such frameworks is that ML complex operators need to be revisited with suitable underlying FHE libraries from existing standards. In this talk, we present how these libraries vary in supported computation operators, computational complexity and memory demands. Those in-turn introduces latency and throughput challenges, especially on resource-constrained edge nodes. For example, SIMD supported CKKS(Cheon-Kim-Kim-Song) library with packing and approximations is known to be the best choice for encrypted ML. However, analysis shows leveled CKKS is limited in implementing complex operators. Further, to avoid accuracy drop associated with approximations, Torus FHE library(TFHE) can be a better choice for certain ML implementations, but suffers from serious performance bottlenecks. Finally, we present an integrated framework FHEMaLe to perform encrypted ML processing with suitable choice of library based on model architecture, desired accuracy, and platform preference as inputs.

Biography:

Dr Ayantika Chatterjee is currently working as an assistant professor at Advanced Technology Development Centre (ATDC), IIT Kharagpur, and also associated with Centre of Excellence in Artificial Intelligence, IIT Kharagpur. She had received her Ph.D and M.S degree in Computer Science and Engineering and Information Technology respectively from IIT Kharagpur. After Ph.D, she joined Data Storage Institute, Agency of Science Technology and Research (A*Star), Singapore as a scientist where she worked in the domain of encrypted database design. She had also worked as a post-doctoral fellow in Indian Statistical Institute, Kolkata. Her research interests include cloud and data security, encrypted computation and analytics and hardware implementation of cryptographic algorithms.

Professor

Department of Electronics, Microelectronics, Computer and Intelligent Systems, University of Zagreb

Croatia

 Abstract:

Side-channel attacks (SCAs) have been a realistic threat to the security of embedded devices for nearly three decades now. Deep learning-based side-channel attacks (DLSCA) entered the field in recent years with the promise of more competitive performance and improved attackers' capabilities compared to other techniques. Indeed, breaking targets protected with countermeasures, even with a few attack traces, and the relaxations on the pre-processing requirements make DLSCA a powerful option. Despite such results, challenges remain. This talk will discuss several of the open challenges and potential future research directions.

Biography:

Dr Stjepan Picek is a full professor at the University of Zagreb, Faculty of Electrical Engineering and Computing, Croatia. He also holds an associate professor position at Radboud University, Nijmegen, and an adjunct professor position at the University of Bergen, Norway. His research interests include security and cryptography, machine learning, and evolutionary computation. To date, Stjepan has given more than 50 invited talks and published more than 150 refereed papers. He is a program committee member and reviewer for a number of conferences and journals, and a member of several professional societies. His work has been featured in the mainstream media and on popular technology blogs. He is a member of ELLIS and a Fellow of the Young Academy of Europe.