Sec-NoC: A Lightweight Secure Communication System for On-Chip Interconnects

Abstract

Multi-Processor Systems-on-Chips (MPSoCs) combine multiple hardware Intellectual Property (IP) components on a single chip. With the rising popularity of fabless manufacturing and agile development, the use of third-party IP for design is becoming more accepted. However, such practice can sometimes significantly compromise the security and reliability of SoC computing systems. Modern Tiled Chip Multi-Processors (TCMPs) employ multi-hop packet-based Network-on-Chip (NoC) as their communication backbone due to their low-latency, high-bandwidth, and scalable topology. During packet transfer through unencrypted NoC, the compromised applications can leak some packets and send them to the outside world through a colluding application. In this talk we talk about Sec-NoC that integrates the notions of lightweight symmetric cryptography to facilitate confidentiality, elliptical curve cryptography to facilitate key exchange mechanisms and authentication, and a lightweight MAC producer to ensure integrity and authentication in TCMP communications.

Biography

Dr. John Jose is a Professor in the Department of Computer Science & Engineering, Indian Institute of Technology Guwahati, where he joined as an Assistant Professor in 2015. He completed his Ph.D degree from Indian Institute of Technology Madras in the field of computer architecture. He is the recipient of the prestigious Qualcomm Faculty Award 2021 and COMSYS Young Achiever Award 2024 for his teaching, research and outreach education contributions in the field of computing systems. He served as the Vice-Chair of IEEE India Council for a period of 3 years. His research group in Multicore Architecture and Systems (MARS) Lab at IIT Guwahati explores the domain of on-chip communication and memory management techniques for large multicore systems, IoT/embedded system security, hardware accelerators for AI and ML applications, disaggregated storage systems and communication support for future quantum cores.  He has over 70 IEEE & ACM peer-reviewed conference publications, over 30 ACM & IEEE transaction papers, as well as Springer and Elsevier journal papers, to his credit. He is a reviewer for many national and international peer-reviewed journals and a member of the technical program committee and organizing committee for many IEEE/ACM national and international conferences.