When Optimization Breaks Security: Architecting Efficient And Trustworthy Hardware by Jeonghyun Woo

Abstract
Modern computing rests on a hardware foundation that must be both efficient and trustworthy. Yet, the very optimizations that make hardware faster, denser and cheaper can erode the security that the entire software stack depends on. Worse, defences retrofitted onto already-deployed hardware are often costly or incomplete, and can even open new attack surfaces. This talk argues that efficiency and security must be co-designed, using RowHammer, a prominent DRAM vulnerability, as the running example.

I will first show how to bypass advanced RowHammer defences previously regarded as secure, and introduce principled mitigations that restore robust protection at minimal performance overhead. I will then demonstrate that even these mitigations can inadvertently create exploitable timing side channels, and present comprehensive defences that close them. Extending beyond memory, I will show how hardware faults directly threaten Al safety through PrisonBreak, the first hardware-induced jailbreak of safety-aligned LLMs, which subverts billion-parameter models with fewer than 25 targeted bit flips. I will conclude by outlining a research agenda along four directions: efficient and trustworthy LLM-serving infrastructure, efficient and secure emerging-memory architectures, stronger and broader confidential computing, and Al-driven hardware assurance and adaptive defence. Together, these directions aim to make hardware efficient and trustworthy by design, ready to anchor the next generation of computing.

About the Speaker
Jeonghyun Woo is a final-year PhD candidate in Electrical and Computer Engineering at the University of British Columbia, advised by Prof. Prashant Nair. His work has directly shaped the security landscape of DRAM memory systems, with contributions that have influenced the designs of leading memory companies, and extends to Al safety through the first demonstration of a hardware-induced jailbreak of large language models. His research has been recognized with the Best Paper Award at HPCA 2023 and the Distinguished Artifact Award at HPCA 2025. He publishes at top computer architecture venues including ISCA and HPCA, and has held research internships at NVIDIA Research and Micron Technology.