A hearty welcome to my homepage.
K. G. Smitha, is a Lecturer at School of Computer Science and
Engineering (SCSE) in Nanyang Technological University (NTU).
K. G. Smitha received her B.Tech. degree in
Electrical and Electronics Engineering from Calicut University, India in
2002, the M.E degree from Anna University, India in 2004 and PhD degree from
Nanyang Technological University (NTU), Singapore in 2010. She was a Lecturer
in Amrita Viswavidaypeetham, Coimbatore, India from
May 2004 to November 2004. She joined School of Computer Engineering at NTU,
Singapore, as a Postdoctoral Research Fellow in September 2009 and later as a
Research Fellow for Teaching in 2013. Her main research interests are in the
areas of low complexity and high speed DSP circuits
computer arithmetic, cognitive radio and signal processing for brain-computer
ADVANCED COMPUTER ARCHITECTURE
tool to convert assembly code to 32-bit MIPS instruction in a single click.
Get the better understanding of cache and virtual memory process from this
simulator. This is simulator illustrates Direct Map Cache, Fully Associative
Cache, 2-way and 4-way set associative cache, also virtual memory. This
simulator is also equipped with 3 types of replacement policy (FIFO, LRU,
The simulator is equipped by Cache Type Analysis to compare different type of
cache and load it into a graph (there is a chart icon on the top-left Cache
Type Analysis Page).
Have fun and please contact Aryani
(firstname.lastname@example.org) for bugs and feedbacks.
MARS Plug-in for pipelined simulation and branch explainer (PSBE)
tool to simulate pipelined MIPS along with various branch prediction schemes (example)
Get better understanding of MIPS 32 bit processor operation(SINGLE CYCLE) using this simulator.
Have fun and please contact Gerald
(email@example.com) for bugs and feedbacks.