Chemical mechanical polishing (or planarization) is an enabling technology which is widely used in the Semiconductor industry to ensure the optimal "flatness" of a wafer before the next level of information is added. The current process involves a held wafer being rotated against a rotating polyurethane pad in an orbital fashion. Slurry containing additives and typically silica or ceria particles is used to abrasively remove material from the wafer surface.
There are a wide range of issues which can affect the performance of chemical mechanical polishing, the below figure illustrates the majority of them.

The main issues currently facing the semiconductor industry are:

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Wafer scratching caused by loose diamonds from the pad conditioner,

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Non-uniformity across the wafer surface, and

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Inadequate determination of the process end-point leading to over or under polishing.

 

bulletMatlab software
bulletDI Dimension AFM
bulletTaylor Hobson Talyscan 150
bulletLogitech CMP machine (Micro machines Centre)

 

bulletModeling of the CMP process to predict wafer topographic variation.
bulletDevelopment of a predictive end-point detection system
bulletNext Generation Planarization Technology

 

The Modeling of Chemical Mechanical Polishing  

Candidate: Miss Wu Lixiao: 

Start : Oct 2002

The aim of this research is to identify the various wavelength components in a wafer surface and use that information to predict the topography of the wafer after planarization under a given set of polishing parameters. By identifying the commonality between blanket and polished wafers it should be possible to develop a more robust technique for qualifying the CMP process.

 

Application and Optimization of the Direct Polish STI CMP Process on 0.1 micron Devices*

Candidate: Mr Wang Sim Kit 

Start: Jun 2002

This project is aimed at using a methodology that can be implemented with or without the end point detection system to predict the optimal process time for the CMP process based on the hypothesis of contact mechanics. It can capture the variation of incoming wafer thickness, material removal rate and the erratic behavior of the process. The research can also serve as a comprehensive framework for better recipe development. Experimental work has shown that this approach demonstrates promising results in reduction of the target mean film thickness variation and works well with different layers and device.

Companies which have provided support include Chartered Semiconductor Manufacturing,

 3M and TECH Semiconductors

 

Title Student Completed Degree

The investigation and optimisation of in-process dressing of chemical mechanical polishing

 Zaw Moe Aung 2003 MSc
Development of a novel pad conditioner for CMP Law Kai Man May 2004 BEng(Hons)

 

  1. Sim Kit Wang, Dong Seng Liu, Feng Chen, David Lee Butler, "The Evaluation and Modeling of the Chemical Mechanical Planarization (CMP) Removal Rate for Polysilicon" , NanoTech 2004, Singapore July 2004

  2. Sim Kit Wang, Cing Gie Lim, Feng Chen And David Lee Butler, "Couple effect of largest ceria abrasive size and pressure on direct STI CMP", Symposium on Microelectronics 2004, IME, Singapore, June 2004

  3. Wang Sim Kit, Chen Feng, Lim Cing Gie, Butler D.L., "Effect of Polymer in Ceria Based Slurry on Chemical Mechanical Planarization (CMP) Removal Rate", AVS Fifth International Conference on Microelectronics and Interfaces, San Francisco, March 2004

  4. L.X. Wu, D.L.Butler, S.K.Wang, "Study of the Velocity and Pressure Effect in the Uniformity of Material removal Rate on Wafer in the Chemical Mechanical Polishing Process", ICoPE 2003/04, Singapore, March 2004

  5. Chen Feng, Wang Sim Kit, Lim Cing Gie, David Chen Hsi-Hsin, Albert Lau, Richard Lee, Edwin Goh, David Lee Butler, " Direct STI CMP with Ceria Based Slurry for 90nm Technology", Proc. VMIC Conf., pp113-120, 2002.

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