|Workshop on Compact Modeling at the 11th International Conference on Modeling and Simulation of Microsystems|
|June 3-4, 2008|
|Venue||Hynes Convention Center
Boston, Massachusetts, USA
(CMs) for circuit simulation have been at the heart of CAD tools for circuit
design over the past decades, and are playing an ever increasingly important
role in the nanometer system-on-chip (SOC) era. As the mainstream
MOS technology is scaled into the nanometer regime, development of a truly
physical and predictive compact model for circuit simulation that covers
geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes
a major challenge.
Workshop on Compact Modeling (WCM) is one of the first of its kind in bringing people in the CM field together. The objective of WCM is to create a truly open forum for discussion among experts in the field as well as feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development and deployment, within the main theme - compact models for circuit simulation, which are largely categorized into the following groups:
|Evening Panel||An evening
Discussion is planned for Tuesday, 7:30-9:00pm.
Whatever your design goals, to achieve them in silicon you must account for manufacturing variation in your design. A typical foundry collects a huge amount of information on process variation. But this information is not available to the circuit designer in a form that can be used to make design decisions.
Compact models have traditionally come with fixed corner files which are useful predicting best and worst case delays of static CMOS logic but not appropriate for other types of circuits or other circuit characteristics. Each member of the Panel will address two board questions from the perspective of their own experience.
- What information does the circuit designer need to know in order to design products which meet their design goals across the whole process window.
- How can this information be delivered
to and used by the circuit designer.
|Josef Watts, IBM, USA|
Program has been posted below and at the following web:
There are 33 contributed papers in
presentations will be 20min including Q&A. Contributed
papers will NOT have oral briefings.
See Nanotech website for instructions for authors:
See Nanotech website for conference registration:
presentation slides will be posted after the conference.
(Click on each to download the PDF file. © Copyright of the PDF files belongs to the respective contributors. Last update: Sept. 9.)
Download and save the entire ZIP file of presentation slides (12MB)
B. M. Klaassen, JUNCAP2 Express: an extremely efficient evaluation
of the JUNCAP2 model
V. K. Dasarapu, Process Aware Compact Model Parameter Extraction for 45 nm Process
C. Enz, Compact Modeling of Noise in non-uniform channel MOSFET
N. Lu, Modeling of Spatial Correlations in Process, Device, and Circuit Variations
T. Fjeldly, Capacitance modeling of Short-Channel DG and GAA MOSFETs
X. Zhou, New Properties and New Challenges in MOS Compact Modeling
G. J. Zhu, Unified Regional Surface Potential for Modeling Common-Gate Symmetric/Asymmetric Double-Gate MOSFETs with Quantum- Mechanical Effects
G. J. Zhu, Quasi-2D Surface-Potential Solution to Three-Terminal Undoped Symmetric Double-Gate Schottky-Barrier MOSFETs
M. Mirua-Mattausch, Construction of a Compact Modeling Platform and Its Application to the Development of Multi-Gate MOSFET Models for Circuit Simulation
G. J. Zhu, Unified Regional Surface Potential for Modeling Common-Gate Symmetric/Asymmetric Double-Gate MOSFETs with Any Body Doping
M. Chan, Surface Potential versus Voltage Equation from Accumulation to Strong Region for Undoped Symmetric Double-Gate MOSFETs and Its Continuous Solution
T. Gneiting, Adaptable Simulator-independent HiSIM2.4 Extractor
Y. Zhou, Source/Drain Junction Partition in MOS Snapback Modeling for ESD Simulation
M. Schroter, Improved layout dependent modeling of the base resistance in advanced HBTs
B. Tudor, An Accurate and Versatile ED- and LD-MOS Model for High-Voltage CMOS IC Spice Simulation
S. Martinie, Analytical Modelling and Performance Analysis of Double-Gate MOSFET-based Circuit Including Ballistic/quasi-ballistic Effects
H. Abebe, Compact Models for Double Gate MOSFET with Quantum Mechanical Effects using Lambert Function
T. Nakagawa, Comparison of Four-terminal DG MOSFET Compact Model with Thin Si channel FinFET Devices
P. Martin, MOSFET Compact Modeling Issues for Low Temperature (77 K - 200 K) Operation
|Websites for Proceedings||http://www.nsti.org/procs/Nanotech2008v3/7
|WCM2007 website||View 2007 WCM program and presentation slides|
|WCM2006 website||View 2006 WCM program and presentation slides|
|WCM2005 website||View 2005 WCM program and presentation slides|
|View 2004 WCM program and presentation slides|
|WCM2003 website||View 2003 WCM program and presentation slides|
|WCM2002 website||View 2002 WCM program and presentation slides|
|(Updated: Sept. 8, 2008)|