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Click here for the WCM2003 official website at NanoTech2003
Workshop on Compact Modeling at the 6th International Conference on Modeling and Simulation of Microsystems
February 25-27, 2003
Venue Grand Hyatt San Francisco
San Francisco, California, USA
Synopsis Compact Models (CMs) for circuit simulation have been at the heart of CAD tools for circuit design over the past decades, and are playing an ever increasingly important role in the very-deep-submicron/system-on-chip (VDSM/SOC) era.  As the mainstream MOS technology is scaled into the VDSM regime, development of a truly physical and predictive compact model for circuit simulation that covers geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major challenge.

Workshop on Compact Modeling (WCM) is one of the first of its kind in bringing people in the CM field together.  The objective of WCM is to create a truly open forum for discussion among experts in the field as well as feedback from technology developers, circuit designers, and CAD tool vendors.  For WCM-MSM2003, it is planned to have an Invited-Speaker Session, an Evening Forum on "Model development - industry requirement dialogue", contributed Poster Session as well as Tutorial Session.  The topics are extended to the following areas, within the main theme - compact models for circuit simulation:

  • Bulk MOS intrinsic models
  • SOI/double-gate MOS models
  • Bipolar/HBT/SiGe models
  • RF/noise/scalable capacitance/NQS models
  • Statistical/predictive/process-based models
  • Interconnection/passive device models
  • Extrinsic/parasitic element models
  • Reliability/hot carrier/tunneling models
  • Atomic-level/quantum-mechanical compact models
  • Numerical/TCAD/behavioral/table-based models
  • Model parameter extraction and optimization
  • Model-simulator interface and standardization
Invited Speakers Invited speakers as well as panelists for the WCM Forum from all over the world (10 countries) are listed below (speakers underlined):
  • Narain Arora, Cadence Design Systems, USA
  • Peter Bendix, LSI Logic, USA
  • Mansun Chan, Hong Kong University of Science and Technology, Hong Kong
  • Robert Dutton, Stanford University, USA
  • Jerry Fossum, University of Florida, USA
  • Carlos Galup-Montoro and Marcio Schneider, Universidade Federal de Santa Catarina, Brazil
  • Gennady Gildenblat and Xin Gu, Pennsylvania State University, USA
  • Thomas Gneiting, Advanced Modeling Solutions, Germany
  • Hermann Gummel, Averill Bell, and Kumud Singhal, Agere Systems, USA
  • Chenming Hu*, Ali Niknejad, and Xuemei Xi, University of California at Berkeley, USA; (*also with Taiwan Semiconductor Manufacturing Company)
  • Dirk Klaassen and Jeroen Paasschens, Philips Research Laboratories, The Netherlands
  • Shiuh-Wuu Lee, Intel, USA
  • Colin McAndrew*, Wladyslaw Grabinski**, and Laurent Lemaitre**, Motorola, *USA, **Switzerland
  • Marek Mierzwinski, Tiburon Design Automation, USA
  • Mitiko Miura-Mattausch, Hiroshima University, Japan
  • Andrea Pacelli, State University of New York at Stony Brook, USA
  • Mahesh Patil, Indian Institute of Technology - Bombay, India
  • Greg Rollins, Mentor Graphics, USA
  • Michael Schroter, University of Technology Dresden, Germany
  • Hyungcheol Shin, Korea Advanced Institute of Science and Technology, Korea
  • Bogdan Tudor, Synopsys, USA
  • Eric Vittoz, Christian Enz, and Francois Krummenacher*, Swiss Center for Electronics and Microtechnology, *EPFL, Switzerland
  • Simon Wong, Niranjan Talwalkar, and Patrick Yue, Stanford University, USA
  • Cary Yang and Sang-Pil Sim, Santa Clara University, USA
  • Xing Zhou, Nanyang Technological University, Singapore
There are 22 invited papers, which are categorized in the following topic areas (speakers underlined):

Compact modeling and design:

Bulk MOS intrinsic models: SOI/double-gate MOS models: Bipolar models: RF/noise models: Interconnection/passive device models: Extrinsic/parasitic element models: Model parameter extraction and optimization Model-simulator interface and standardization
Forum and Evening Panel  Forum on Model development - industry requirement dialogue

Continued from the first successful Workshop on Compact Modeling (WCM-MSM2002) in San Juan, April 2002, this second Workshop (WCM-MSM2003) encompasses a broader range of topics, from intrinsic bulk MOS to bipolar and SOI/double-gate, as well as RF/interconnect/extrinsic/passive-element models, covering important issues on design considerations, parameter extraction, and simulator interface.  To complement the invited technical presentations by experts from both academia and industry, a Forum on "model development - industry requirement dialogue" is organized, in which we are going to hear experts' views on the general topic:

The Role of Compact Model in the Fab and Fabless Business

An Evening Panel discussion will be followed by a panel of experts from major representative academic (Stanford, UC Berkeley), chip industry (Intel, LSI Logic, Philips), and EDA vendors (Cadence, Mentor Graphics, Synopsys).  The Panel will discuss important topics that are in line with the theme of this Workshop:
- Key to bridging compact-model development to designers and simulator vendors
- Current needs and priorities in compact-model development
- Intrinsic model with respect to extrinsic, parasitic, passive, and interconnect models
- Model interface to simulators, extractors, and users

We are expected to hear "spirited difference of opinions" on how to define, develop, and deploy a good compact model that is central to the mutual benefit of the entire chip design, modeling, and manufacturing communities.

Moderator Narain Arora, Cadence Design Systems, USA
  • Peter Bendix, LSI Logic, USA
  • Robert Dutton, Stanford University, USA
  • Dirk Klaassen, Philips Research Laboratories, The Netherlands
  • Shiuh-Wuu Lee, Intel, USA
  • Ali Niknejad, University of California at Berkeley, USA
  • Greg Rollins, Mentor Graphics, USA
  • Bogdan Tudor, Synopsys, USA
  • top
    Poster Session Poster presentations in the scope of "compact models for circuit simulation" are solicited.  A 5-minute oral briefing for each poster paper is planned before the poster presentation session.

    Contributed poster papers are listed below (presenters underlined):

    Tutorial Session Two tutorials are offered as listed below (speakers underlined): top
    (Click on each  to download the PDF file.  © Copyright of the PDF files belongs to the respective contributors.  Last update: April 17, 2003.)
    Download and save ...Download and save the entire ZIP file of presentation slides (14MB)

    View SlidesXing Zhou, Openning Remark

    Invited papers View SlidesNarain Arora, Characterization and Modeling of Copper Interconnects for VLSI Design
    View SlidesAverill Bell, USIM Design Considerations
    View SlidesMansun Chan, A Framework for Generic Physics Based Double-Gate MOSFET Modeling
    View SlidesJerry Fossum, A Physics-Based Compact Model for Nano-Scale DG and FD/SOI MOSFETs
    View SlidesCarlos Galup-Montoro, Theory, Development and Applications of the Advanced Compact MOSFET (ACM) Model
    View SlidesThomas Gneiting, A Unified Environment for the Modeling of Ultra Deep Submicron MOS Transistors
    View SlidesXin Gu, Surface-Potential-Based Extrinsic MOSFET Model
    View SlidesDirk Klaassen, Noise Modelling with MOS Model 11 for RF-CMOS Applications
    View SlidesLaurent Lemaitre, Standardization of Compact Device Modeling in High Level Description Language
    View SlidesColin McAndrew, BJT Modeling with VBIC, Basics and V1.3 Updates
    View SlidesMarek Mierzwinski, Changing the Paradigm for Compact Model Integration in Circuit Simulators Using Verilog-A
    View SlidesMitiko Miura-Mattausch, HiSIM: Accurate Charge Modeling Important for RF Era
    View SlidesAli Niknejad, Compact Modeling for RF and Microwave Integrated Circuits
    View SlidesMichael Schroter, Compact Bipolar Transistor Modeling - Issues and Possible Solutions
    View SlidesSang-Pil Sim, Unified RLC Model for On-chip Interconnects 
    View SlidesHyungcheol Shin, Physical Modeling of Substrate Resistance in RF MOSFETs
    View SlidesEric Vittoz, A Basic Property of MOS Transistors and its Circuit Implications
    View SlidesXing Zhou, A Technology-Based Compact Model for Predictive Deep-Submicron MOSFET Modeling and Characterization
    Forum The Role of Compact Models in the Fab and Fabless Business
    View SlidesColin McAndrew (Session Chair)
    View SlidesPeter Bendix, The Role of Compact Models in the Fab and Fabless Business
    View SlidesDirk Klaassen, The Role of Compact Models in the Fab and Fabless Business
    View SlidesShiuh-Wuu Lee, Physical Compact Modeling
    Posters View SlidesSiau Ben Chiah, Unified Length-/Width-Dependent Threshold Voltage Model with Reverse Short-Channel and Inverse Narrow-Width Effects
    View SlidesSiau Ben Chiah, Unified Length-/Width-Dependent Drain Current Model for Deep-Submicron MOSFETs
    View SlidesXin Gu, Substrate Current in Surface-Potential-Based Compact MOSFET Models
    View SlidesXin Gu, Application of Genetic Algorithm to Compact MOSFET Model Parameter Extraction
    View SlidesXin Gu, A Surface-Potential-Based Compact Model of NMOSFET Gate Tunneling Current
    View SlidesTadashi Nakagawa, Primary Consideration on Compact Modeling of DG MOSFETs with Four-Terminal Operation Mode
    View SlidesAndrzej Napieralski, An Interactive Website as a Tool for CAD of Power Circuits
    View SlidesQuoc Ngo, Gate Current Partitioning Scheme for Circuit Simulation
    View SlidesRichard Williams, A Compact Model Methodology for Device Design Uncertainty
    Tutorials View SlidesJeroen Paasschens, Modelling of Si and SiGe Bipolar Transistors with the Compact Model Mextram 504
    View SlidesMahesh Patil, The Look-Up Table Approach and its Implementation in a Circuit Simulator
    Websites for Proceedings
    (Vol. 2, Chapter 7: Compact Modeling)
    official websites
    WCM2002 website View 2002 WCM program and presentation slides

    Download PDFClick to download the program (PDF) (Updated: February 11, 2003)