Session 8: Modeling and Simulation – High-Frequency and Multi-Gate Device Modeling
Monday, December 6, 1:30 p.m.
Co-Chairs: Shinji Odanaka, Osaka University
This work presents compact models for both cases of without and with the high conductivity buried layer in dual-well bulk CMOS, which can be employed for keep away radius estimation. A comparative analysis of the coupling noise due to TSV in both dual-well bulk CMOS and PD-SOI is presented
A modeling methodology has been demonstrated for SOI substrates for use in RF front end circuits. It has been shown that the use of a varactor to model the BOX capacitor improves the harmonic distortion predictions from simulations for circuits in RF/Analog applications.
In this work, we present the first surface-potential based compact model for RF GaN HEMTs, and benchmark our work against both numerical simulations and device measurements. It is expected that such an approach will be superior to other modeling techniques in terms of scalability and model performance for applications where accurate distortion modeling is of paramount importance.
We derive a new compact expression for the effective FinFET gate resistance and validate it on experimental data. Moreover, a model for FinFET thermal noise is presented, which predicts measured data accurately. It is demonstrated that the observed increase of drain current noise with drain-source voltage is not due to microscopic excess noise, but to the access resistances which modify the transfer of channel thermal noise to the terminals.
A detailed study of the impacts of fin aspect ratio and crystalline orientation and process-induced channel stress on the performance of multi-gate transistors is presented. It is found that CESL-induced stress provides for the greatest enhancement in carrier mobility and ballistic velocity, for n- and p-channel FinFETs and Tri-Gate FET structures. Extracted carrier velocity values in short-channel FinFETs still largely depend on carrier mobility.
In this paper the performances of Si NW FETs in the presence of electron-phonon scattering are investigated using a quantum transport solver. Two important device metrics, the low-field mobility and the injection velocity are computed and analyzed in n- and p-doped NW FETs with , , and  transport.
We have demonstrated that extraordinary high pH sensitivity (far above the Nernst limit) can be achieved with DGFET device and this sensitivity gain can be used to counteract the screening limits of DNA detection. Back gate operation shows signal amplification due to its asymmetric thickness of top/back oxide.