2007 IEDM

Session 21: Modeling and Simulation - Development and Applications of Compact Models for Advanced Circuits
Tuesday, December 11, 2:15 p.m.
Lincoln Room
Co-Chairs: Dirk Klaassen, NXP Semiconductors
Srinivas Jallepalli, Freescale Semiconductor

2:15 p.m.

2:20 p.m.
21.1  A Unified Compact Model of the Gate Oxide Reliability for Complete Circuit Level Analysis, C-H Lee, G-Y Yang, J-K Park, Y-K Park, B-S Yoo, H-W Kim, D. Park, M-H Yoo, Samsung Electronics Co., Ltd.
A unified compact model to predict the performance degradation of a circuit due to the electrical gate oxide stress is developed and verified by experimental results. HCI, Off-State, and FN degradations can be described by a single formula which models the trap generation over the stress time and voltage.

2:45 p.m.
21.2  A Predictive Analytical Model of 3D MIM Capacitors for RC IC, N. Segura, S. Cremer, D. Gloria, L. Ciampolini, E. Picollet and M. Minondo, STMicroelectronics
This paper reports a predictive analytical transmission RLC model of 3D MIM capacitors in a 0.13 µm BICMOS technology. The aim of this predictive model is to help circuit design with compatible CPU time. It allows adjusting process parameters in order to optimize electrical features. The model has been compared with electromagnetic simulations and S-parameters measurements up to 42GHz.

3:10 p.m.
21.3  Physically-Based Unified Compact Model for Low-Field Carrier Mobility in MOSFETs with Different Gate Stacks and Biaxial/Uniaxial Stress Conditions, S. Reggiani, L. Silvestri, A. Cacciatori*, E. Gnani, A. Gnudi, G. Baccarani, University of Bologna, *University of Brescia
A compact model of the low-field effective carrier mobility is developed for n- and p-type MOSFETs with either polySi or TiN gate, ultrathin SiO2/HfO2 gate stacks, and silicon under biaxial or uniaxial stress conditions. Physical insights, theoretical analyses and experimental investigations are used to develop and accurately calibrate the model

3:35 p.m.
21.4  A New Model for 1/f Noise in High-k MOSFETs, T. Morshed, S.P. Devireddy, M.S. Rahman, Z. Celik-Butler , H.-H. Tseng*, A. Zlotnicka**, A. Shanware^, K. Green^, J.J. Chambers^, M.R. Visokay^, M.A. Quevedo-Lopez^ and L. Colombo^, University of Texas, *Sematech, **Freescale Semiconductor, ^Texas Instruments
A new model based on correlated number-mobility fluctuations is proposed to model the 1/f noise in MOSFETs with multi-stack gate dielectrics. The model accounts for the non-uniformity in the dielectric trap profile, and accurately predicts the noise in two different high-k MOSFETs with varying interfacial layers at all tested temperatures.

4:00 p.m.
21.5  A Multi-Gate MOSFET Compact Model Featuring Independent-Gate Operation, D.D. Lu, M.V. Dunga, C.-H. Lin, A.M. Niknejad and C. Hu, University of California
A compact model for independent double gate MOSFETs is developed. The core model is verified against TCAD simulations without using any fitting parameters. Numerous real device effects are captured. We also illustrate its use in the simulation of independent-gates SRAM cells and tuning out device variations through back gate biasing.

4:25 p.m.
21.6  High Performance CMOS Variability in the 65nm Regime and Beyond (Invited), S. Nassif, K. Bernstein, D. Frank, A. Gattiker, W. Haensch, B. Ji, E. Nowak, D. Pearson, N. Rohrer, IBM

4:50 p.m.
21.7  Rapid Circuit-based Optimization of Low Operational Power CMOS Devices, P. Christie, A. Nackaerts*, T. Hoffmann, A. Kumar, NXP Semiconductors, *IMEC
This paper describes the use of a rapid design flow to co-design low operational (static + dynamic) power transistors embedded within a 16-bit multiplier circuit. Our approach was based on a reduced order compact model specifically designed for parameter extraction from TCAD-generated IV curves. The resulting multiplier circuit dissipated 84% less power than the reference design.