2005 IEDM

Session 9: Modeling and Simulation Compact Models
Monday, December 5, 1:30 p.m.
Thoroughbred Room

Co-Chairs: Kuntal Joardar, Texas Instruments
Jeong-Taek Kong, Samsung Electronics Co. Ltd.

1:30 p.m.
Introduction

1:35 p.m.
9.1  A New Compact Model for Junctions in Advanced CMOS Technologies, A.J. Scholten, G.D.J. Smit, M. Durand, R. van Langevelde, C.J.J. Dachs, D.B.M. Klaassen, Philips Research Laboratories, Eindhoven, The Netherlands

We have developed a new compact model for the junction capacitances and leakage currents in deep-submicron CMOS technologies. The model is more physical and more accurate than existing models, and contains Shockley-Read-Hall, trap-assisted tunneling, band-to-band-tunneling, and avalanche breakdown. It has been validated for a wide range of bias and temperature, for NMOS and PMOS junctions, and for different CMOS generations. Application areas are clearly identified.

2:00 p.m.
9.2  High Performance, sub-50nm MOSFETS for Mixed Signal Applications, V. Dimitrov, J. Heng, K. Timp, O. Dimauro, R. Chan, J. Feng, W. Hafez, T. Sorsch*, W. Mansfield*, J. Miner*, A. Kornblit*, F. Klemens*, J. Bower*, R. Cirelli*, A. Taylor*, M. Feng, G. Timp, University of Illinois, Urbana, IL, *New Jersey Nanotechnology Consortium, Murray Hill, NJ

We have fabricated and tested sub-50nm gate length nMOSFETs with fT up to 290GHz to assess their suitability for mixed signal applications in the super high frequency (SHF) band, i.e. 3-30GHz. We have also developed an accurate, high frequency (1-50GHz) model suitable for integration with digital CMOS.

2:25 p.m.
9.3  High-Voltage LDMOS Compact Model for RF Applications, M.B. Willemsen, R. van Langevelde, Philips Research Laboratories, Eindhoven, The Netherlands

A new compact model for circuit design of high-voltage RF LDMOS transistors has been developed. The new model results in a sound physical solution for the internal drain voltage, and modeled DC-characteristics, Y-parameter bias-sweeps (including fT) in good agreement with device simulations and measurements for all operating conditions.

2:50 p.m.
9.4  Physics-Based Noise Modelling of Semiconductor Devices in Large-Signal Operation Including Low -Frequency Noise Conversion Effects (Invited), G. Ghione, F. Bonani, S. Donati, F. Bertazzi, G. Conte, Politecnico di Torino, Torino, Italy

The paper presents a review on physics-based noise modelling of semiconductor devices, with emphasis on large-signal noise simulation in periodic device operation and on related low-frequency noise conversion effects. The impact of physics-based noise modelling on the development of compact device models for circuit simulation is also discussed.