Session 36: Modeling and Simulation Compact Modeling

Wednesday, December 10, 1:30 p.m.
Georgetown Room

Co-Chairs: Rafael Rios, Intel Corporation
Ronald van Langevelde, Philips Research

1:30 p.m

1:35 p.m.
36.1  Reemergence of the Surface-Potential-Based Compact MOSFET Models, G. Gildenblat, X. Cai, T.L. Chen, X. Gu and H. Wang, The Pennsylvania State University, University Park, PA

Surface-potential-based approach is examined as a foundation for the next generation compact MOSFET models. General considerations of the model structure are exemplified using newly developed advanced surface-potential-based model (SP). The main topic is application of symmetric linearization concept to the drain current, terminal charges and extrinsic model. The work reviews the current status of the field and presents original Results developed within SP context.

2:00 p.m.
36.2  New Compact Model for Induced Gate Current Noise, R. van Langevelde, J.C.J. Paasschens, A.J. Scholten, R.J. Havens, L.F. Tiemeijer and D.B.M. Klaassen, Philips Research Laboratories, Eindhoven, The Netherlands

Accurate compact modeling of induced gate noise is a prerequisite for RF CMOS circuit design. Existing models underestimate the induced gate noise for short-channel devices. Here, a new model is introduced, based on an improved Klaassen-Prins approach, which accurately accounts for velocity saturation. The model accurately describes noise without fitting any additional parameters.

2:25 p.m.
36.3  Hydrodynamic Modeling of RF Noise in CMOS Devices, C. Jungemann, B. Neinhues*, C. D. Nguyen*, B. Meinerzhagen*, R. W. Dutton, A. J. Scholten** and L. F. Tiemeijer**, Stanford University, Stanford, CA, *Institute fur Theoretische Elektrotechnik und Mikroelektronik, Universitat Bremen, Germany and **Philips Research Laboratories, Eindhoven, The Netherlands

A new hydrodynamic noise model for CMOS devices including a quantum correction for the inversion layer is validated by comparison with experiments. Noise in non-classical ultra-short channel devices is investigated and found to be similar to noise in classical bulk MOSFETs.

2:50 p.m.
36.4  Predictive Spiral Inductor Compact Model for Frequency and Time Domain, L.F. Tiemeijer, R.J. Havens, R. de Kort, Y. Bouttement, P. Deixler and M. Ryczek, Philips Research Laboratories, Eindhoven, The Netherlands

In this paper we explain how to predict the inductor performance in the frequency and time domain directly from geometrical and back-end parameters, without any fitting factors or measurements, and present the first scalable equivalent circuit model for integrated symmetric inductors with center tap.

3:15 p.m.
36.5  Voltage and Temperature Dependence of Capacitance of High-K HfO2 MIM Capacitors: A Unified Understanding and Prediction, C. Zhu, H. Hu, X. Yu, A. Chin*, M.F. Li and D.L. Kwong**, National University of Singapore, Singapore and *National Chiao Tung University, Taiwan and **University of Texas, Austin, TX

This work is intended to explain dependences of VCC on dielectric thickness and frequency and temperature dependence of capacitance of HfO2 MIM capacitors. Based on free carrier injection model, a unified understanding is achieved for the first time. This model is applied to predict the VCC for future applications.

3:40 p.m.
36.6  Thermal Analysis of Ultra-Thin Body Device Scaling, E. Pop, R. Dutton and K. Goodson, Stanford University, Stanford, CA

This paper explores the effect of confined dimensions and a more complicated geometry on the self-heating of ultra-thin body SOI and FinFET devices. We show device temperatures are very sensitive to the choice of drain and extension dimensions, and suggest an appropriate parameter design space.

4:05 p.m.
36.7  A Self-Consistent Junction Temperature Estimation Methodology for Nanometer Scale ICs with Implications for Performance and Thermal Management, K. Banerjee, S.-C. Lin, A. Keshavarzi*, S. Narendra* and V. De*, University of California, Santa Barbara, CA and *Intel Corporation, Hillsboro, OR

This work introduces a self-consistent junction temperature estimation method for nanometer scale technologies by taking into account various electrothermal couplings between operating frequency, power dissipation and temperature. The self-consistent solutions of junction temperature are shown to have significant implications for evaluating various power-performance-reliability-cooling cost tradeoffs and can be used to optimize the performance of ICs.