Mixed-Signal Multi-Level Simulation of VLSI Circuits (XSIM)

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Introducing Xsim


Xsim is designed as a true single-engine mixed-mode simulator with a unified structure. It is based on electrical (circuit-level) matrix solution, with event-driven (logic-level) and functional (behavioral-level) techniques as accelerations for digital and analog circuits, respectively. The key to its automatic circuit partitioning and dynamic mode switching capabilities is based on the subcircuit expansion approach in which the higher-level models correspond directly to their equivalent lower-level subcircuits.


Electrical (circuit-level) simulation

- Efficient vector sparse-matrix solution for solving bordered block diagonal (BBD) matrix as a result of subcircuit expansion.

- Implemented device models: diode; MOS level 1, 2, 3; BJT Gummel-Poon; AIM HFET, MESFET, HBT.

- A unified composite bipolar-MOS (BiMOS) model for deep submicron CMOS.

- SPICE netlist compatible.

- Device model bypass and incremental matrix update.

Digital (gate-level) simulation

- Two representations of a logic gate (U card): behavioral (Boolean, .model card) and structural (subcircuit, .subckt card).

- Dynamic delay model based on user-netlist dependent fanout and run-time dependent input transition time:

td = tdi(Ti,Ni,CL) + Reff(Ti,Ni,CL)CL

where td is the gate delay (including low-to-high and high-to-low delays); tdi is the intrinsic (unloaded) delay and Reff is the effective resistance, which are a function of the input transition time Ti and the number of triggered inputs determined at run time; CL is the fanout capacitance determined from user netlist.

- Logic parameters (input and output capacitances and intrinsic delays) are extracted from the low-level subcircuit, either by pre-configuration or during the simulation.

Analog (behavioral-level) simulation

- Built-in behavioral functionals in the SPICE netlist format.

Mixed-signal multi-level simulation

- Mixed-signal: analog and digital circuits can be freely mixed.

- Mixed-level: gate-circuit-behavioral, with gate and behavioral levels as abstractions.

- Mixed-method: sparse-matrix, relaxation, event-driven, selective-trace.

- Mixed-technology: different logic families can be mixed in the same circuit, and the interface will be automatically modeled by full subcircuit to ensure consistency.

Automatic circuit partitioning

- Partitioning of analog and digital blocks is done automatically by the simulator.

- The partitioning can change at run time.

Dynamic mode switching

- Digital gates can be simulated in "analog" mode (equivalent to replacing all U cards by X cards) or "digital" mode (Boolean plus dynamically-extracted delays).

- When the mode is set to "mixed", this switching happens for each gate at run time, based on the input signal quality.

Hierarchical probing

- Node voltages and branch currents at any level can be probed.

- Device internal probes (e.g., BJT internal VBE, MOS substrate diode current) are also available.

  Large digital circuits: Using full "digital" mode for logic synthesis with vendor-supplied delay parameters, and then, subcircuit model for back-annotated timing verification.

Mixed-signal interface circuits: Using "mixed" mode for data-converter systems with large ratio of digital/analog circuitry.

PCB-level system simulation: Large systems with mixed digital (including mixed logic families) and analog functional blocks.