Singapore-MIT Alliance for Research and Technology
Low Energy Electronic Systems - Phase II

1 CREATE Way #09-01/02 CREATE Tower; #01-13 Enterprise Wing Singapore 138602

LEES - The SMART Low Energy Electronic Systems IRG aims to identify new integrated circuit technologies that becomes the new added value for reduced energy per function, lower power consumption and higher performance in our electronics infrastructure. These integrated circuits of the futre are expected to impact applications in wireless communication, power electronics, LED lighting, printing, displays, and computing. The research is performed by teams that have expertise in materials, devices, and circuits, invoking new advances at all levels to produce electronic systems that performe new function while decreasing system energy. The initial technology goals are in the areas of Power Electronic Systems, Efficient Communications, and Multi-fundtional Displays and Lighting Systems.
[News: NRF, Facts, CS-interview]


Compact Modeling for Novel III-V Devices and III-V/Si Hybrid PDK Development

Lead Investigators

  • NTU - Dr Xing Zhou
  • MIT - Dr Dimitri Antoniadis
  • Description

    The project aims to create and interface compact models of new III-V devices into Si CMOS platform.  The compact models for GaN and InGaAs HEMTs and LEDs created in LEES Phase I will be calibrated with LEES processes/devices for use in the hybrid PDK in Phase II.  Novel hybrid PDKs with LEES and foundry processes will be developed for LEES internal designers as well as outside partners.  New models (e.g., heterojunction bipolar transistors (HBTs) for InP/Si platforms in Phase II) will be developed.  Consistent single core model for both III-V and Si devices in one hybrid PDK will be explored with potential commercialization.  The overall goal is to create the best-in-class device core models for III-V/Si integration that aids the early III-V/Si technology development as well as “mixed-device” novel circuit design and performance evaluation, and ultimately, leading a new path to novel modeling infrastructure for novel circuit design and innovation.

    Openings for Research Staff and PhD Scholarships