Numerical Characterization of Nanowire Transistors and Logic Gates with Parametric Variations for Probabilistic-CMOS
(August 2009 --)
This project is directed towards characterizing basic silicon-nanowire (SiNW) transistors and logic gates using numerical simulations in the presence of parametric variations that are inevitable in future devices and technologies. Major device and process parameters prone to random variations can be varied systematically, from which transistor/gate figures of merits (FOMs) can be obtained with detailed physics incorporated in the device simulations. Results of such simulations can be used for validating compact-model (CM) “corner” solutions. As an example, suppose that the SiNW radius, oxide thickness, and gate length are identified as major variables, and their individual and combined variations can be simulated, from which transistor FOMs (such as on/off currents, threshold voltage, transconductance and drain conductance, etc.) at the corner conditions can be obtained. When the same idea is extended to the gate level (e.g., an inverter) using mixed device/circuit simulation, gate-level FOMs (e.g., logic levels, noise margin, delay, static/dynamic power dissipation) can also be obtained due to device parameter variations. Eventually, numerically characterized transistors/gates in the presence of parametric variations can provide the data for CM validation, which can be bridged to the probabilistic-CMOS design paradigm.