Variability Study of Nanowire: A Compact Model Application
(Original Title: Logic/Circuit Design of Futuristic Probabilistic-CMOS)

Machavolu Kamakshi Srikanth
(August 2008 -- May 2009)


As semiconductor technology continues to scale following Moore’s Law, increased power will eventually limit further increase in speed and density.  To sustain technology scaling and prolong the promise the industry has benefited from scaling, one of the novel concepts has been proposed – “probabilistic CMOS” (PCMOS) – that exploits randomness in futuristic devices by taking advantage of probabilistic behaviors into chip designs.  This project is directed towards exploring the basic requirements in achieving logic/circuit design in the new PCMOS paradigm.  By simulating basic logic gates with transistor subcircuits, gate-level parameters (delay, gain, noise margin, power dissipation, etc.) can be related to transistor parameters (on/off currents, threshold voltage, transconductance, subthreshold swing, gate capacitance, etc.), from which technology variations can be studied through model-parameter distributions.  This project will provide the essential link from technology through device to circuit/logic, which is a first step towards technology/circuit co-design in the PCMOS paradigm.