Unified AC Charge and DC Current Modeling for Very-Deep-Submicron CMOS Technology
Siau Ben Chiah
(June 28, 2000 -- Dec 2005)
This project is directed towards the development and implementation of a unified and consistent framework for the design and modeling of ULSI systems in the very-deep-submicron (VDSM) technology era. It will be centered at the circuit level, with transistor compact models describing VDSM device electrical characteristics that can be correlated to process variables; and higher-level gate/block representations that correspond directly and consistently to its subcircuit representation for digital/analog acceleration. Device model parameters will be extracted from technology data such that statistical process fluctuations can be captured and analyzed and their effects on circuit/system performance can be predicted. Analog functional blocks and digital gates will be characterized from their subcircuit equivalent such that analog and digital circuitry can be truly and implicitly mixed with a consistent representation. Ultimately, successful research and development will lead to the approach and solution for circuit designers in first-time silicon success, and a bridge between VDSM technology developers and system designers.
First-year report First-year presentation