Compact Modeling of EPROM Devices
(January 24, 2011 -- )
EPROM devices have been found as ID bits for many Hewlett Packard printing-head products. It has wide applications in industry as memory devices. To design integrated circuits using these device building blocks, a compact model with physical description of their electrical characteristics is essential. Unfortunately, very little research work has been found on EPROM devices since it is challenging to derive a unified set of equations encompassing floating gates with the bulk device. In addition, it is always desirable that the model can predict characteristics due to intentional or unintentional process variations as well as structural asymmetry.
This project is directed towards developing such a unified core model based on existing knowledge of bulk-MOS models. It will be based on the unified regional modeling approach with extension to include various hot carrier injection, electron tunneling, drain breakdown, memory leakage, and process variation effects. The unification of model for various device structures will prove to be of advantage over individual models developed only for a particular structure and operation. Comprehensive numerical simulations and experimental measurements of EPROM devices will be conducted for model validation during the course of this research.