Design, Modeling, and Characterization of Submicron MOSFETs
Khee Yong Lim
(Aug. 2, 1997 -- Jul. 31, 2000. Degree awarded: Sept. 3, 2001)
This project is directed towards the development of an empirical approach to the design, modeling, and characterization of submicron MOSFETs. The objective is to construct a clear and simplified framework that can be used to sequence and segment a design so that circuit, device, and fabricational parameter ranges can be identified. The simplified empirical model can also provide a first attempt at optimization, as well as a guide for detailed device-level simulation and process integration. Based on the evaluation of the empirical formulations, trade-offs can be easily determined for the optimal device design and coupled with the circuit constraints and process windows that can achieve the design. The methodology is to formulate empirical relations between the device parameters (channel length, junction depth, oxide thickness, etc.) and circuit constraints (threshold voltage, saturation current, supply voltage, gate delay, etc.), from which "process box" can be generated that can be used to bracket the final design.
First-year report First-year presentation (1MB)
oral presentation (2.6MB)
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