NTU-TUM Joint PhD Project:Potential candidates: Please contact Dr. Xing ZHOU.
- Project Title: Transistor/Gate-Level Reliability and Variability Modeling
NTU Supervisor: Dr Zhou Xing
TUM Supervisor: Dr Ulf Schlichtmann
Scholarships immediately available for the August 2011 intake.
News about NTU-TUM Program: news1, news2.
The mainstream CMOS industry has been bridged by transistor compact models (CMs) calibrated to the “golden die” from a fab and used by a fabless in the circuit/logic designs. The current chip design/fabrication paradigm is to evaluate the given performance figures-of-merit (FOMs) at various levels by circuit/gate-level simulations based on the “nominal” device model. To meet the performance targets while still maintaining good yield for the real-world situation with intrinsic device degradations and inevitable process variations, the designer checks for reliability and variability by extracting different sets of model parameters of the ‘fresh’-CM to emulate “aging” devices for reliability prediction, and by performing random sampling (or Monte Carlo) simulations with device parametric variations of the ‘deterministic’-CM for the given process windows. This paradigm has been the industry practice for decades and it starts to face increasing challenges due to increased role of reliability/ variability issues as scaling continues. Obviously, research and innovative ideas in reliability/variability modeling are needed in order to maintain chip performance and yield for the coming generations before they become a main showstopper, as well as to pave the way for future generation non-classical CMOS. Reliability and variability have recently been selected as top research priorities by the Semiconductor Research Corporation (SRC) .
This project is directed towards the development of analytic models for reliability and variability of CMOS circuits at the transistor and gate levels. Major reliability issues in MOS transistors will be captured in the physics-based compact models and propagated to the gate-level. A multi-level modeling approach will be adopted in which the higher-level (gate) model corresponds to, and its parameters being extracted from, the lower-level (transistor) equivalent. The ultimate goal is to have device reliability and variability captured and incorporated into the circuit/logic design rather than assessing them after the design based on ideal device characteristics.
The specific aims of this PhD project are
• Develop transistor degradation compact models for use in gate-level aging analysis and timing predictions;
• Apply transistor compact models for statistical parametric variations to gate-level abstraction for use in variability-aware designs.
This joint PhD project will leverage on more than a dozen years of research effort in compact modeling at NTU [Dr Zhou] and the recent relevant project on Compact Model Application to Logic/Circuit Design of Futuristic Probabilistic-CMOS at the Institute for Sustainable Nanoelectronics (ISNE) , with close collaboration with the team at TUM [Dr Schlichtmann] on gate-level reliability/variability modeling . The two teams have been in close interactions since their first contact in 2008 , with recent mutual visits which laid out specific research topics in transistor/gate-level reliability/variability modeling –. Preliminary work will be shared at the special session for Munich–Singapore collaboration of the forthcoming ISIC’09 .
New physical reliability models (such as NBTI and HCI) will be developed and incorporated into our existing model framework, adding a new dimension in “aging” that can be used by the TUM group on gate-level aging analysis. Model parametric variations at the transistor and circuit/gate levels will be studied with statistical and analytical approaches, from which gate-level variability can be built with the Current Source Model (CSM) developed by the TUM team. A multi-level framework linking the two abstract domains of the respective teams will be developed, from which a generic electronic design automation (EDA) framework and a paradigm shift in designing future chips will be explored.
With the ongoing interactions and the resources of the respective NTU and TUM teams, the proposed joint PhD project as well as the researchers represents a unique collaboration to embark on a challenging task for developing future generation design tools and solutions.
 U. Schlichtmann, “Analyzing (and Optimizing) Reliability of ICs,” (Invited Talk), NTU-TUM Forum, Singapore, Sep. 4, 2008.
 C. Knoth, “Versatile Nonlinear Dynamic Models for Logic Cells,” Microelectronics Centre Seminar, NTU, Singapore, Sep. 30, 2009.
 D. Lorenz, “Aging Analysis of Circuit Timing Considering NBTI and HCI,” Research Seminar, TUM, Germany, Oct. 12, 2009.
 X. Zhou, “Compact Modeling Application to Statistical/Probabilistic Technology Variations,” Research Seminar, TUM, Germany, Oct. 13, 2009.
 X. Zhou, G. J. Zhu, S. H. Lin, Z. H. Chen, M. K. Srikanth, Y. F. Yan, R. Selvakumar, W. Chandra, J. B. Zhang, C. Q. Wei, Z. H. Wang, and P. Bathla, “Subcircuit Approach to Inventive Compact Modeling for CMOS Variability and Reliability,” to appear in Proc. ISIC2009, Special Session 9: Munich–Singapore Cooperative Semiconductor and IC Research, Singapore, Dec. 15, 2009.