H. T. Zhou, X. Zhou, and F. Benistant, "An Explicit
Compact Model for High-Voltage LDMOS," International
Conference on Solid State Devices and Materials (SSDM2013),
Fukuoka, Japan, Sep. 2013, Poster PS-14-4.
S. B. Chiah, X. Zhou, and L. Yuan, "Compact Zero-Temperature
Coefficient Modeling Approach for MOSFETs Based on Unified Regional Modeling
of Surface Potential," IEEE Trans. Electron
Devices, Vol. 60, No. 7, pp.
2164-2170, Jul. 2013.
H. T. Zhou, X. Zhou, and F. Benistant, "An Analytical
DC Model for High-Voltage LDMOS," Proc.
of the 7th International Conference on Materials for Advanced Technologies
(ICMAT2013),
Symposium
Y: Reliability and Variability of Devices for Circuits and Systems
[RV-DCS], Singapore, July 2013, Paper
Y6-5.
X. Zhou, J. B. Zhang, B. Syamal, Z. M. Zhu, H. T.
Zhou, and S. B. Chiah, "Top-down Drift-diffusion versus Bottom-up Quasi-ballistic
Formalism in Device Compact Modeling," (Keynote), Proc.
of the 20th International Conference on Mixed Design of Integrated Circuits
and Systems (MIXDES2013),
Gdynia, Poland, Jun. 2013, p. 53.
X. Zhou, J. B. Zhang, B. Syamal, Z. M. Zhu, and L.
Yuan, "A Scalable Compact Model for Generic HEMTs in III-V/Si Co-integrated
Hybrid Design," (Invited Paper), Proc.
of the 9th International Conference on Electron Devices and Solid State
Circuits (EDSSC2013),
Hong Kong, Jun. 2013, paper 299.
X. Zhou, J. B. Zhang, B. Syamal, S. B. Chiah, H.
T. Zhou, and L. Yuan, "Unified Regional Modeling of GaN HEMTs with the
2DEG and DD Formalism," (Invited Paper), Proc.
of the 11th International Conference on Solid-State and Integrated-Circuit
Technology (ICSICT2012), Xi'an, China,
Oct. 2012, paper S21_01.
X. Zhou, S. B. Chiah, and L. Yuan, "A Simplified
Model for Dynamic Depletion in Doped UTB-SOI/DG-FinFETs," (Invited Paper),
Proc. of the NSTI Nanotech (WCM-Nanotech2012),
Santa Clara, CA, Jun. 2012, vol. 2, pp. 784-787.
S. B. Chiah, X. Zhou, Z. H. Chen, H. M. Chen, and
L. Yuan, "Unified Regional Approach to High Temperature SOI DC/AC Modeling,"
Proc. of the NSTI Nanotech (WCM-Nanotech2012),
Santa Clara, CA, Jun. 2012, vol. 2, pp. 796-799.
J. B. Zhang and X. Zhou, "An Analytical 2DEG Model
Considering the Two Lowest Subbands," Proc.
of the NSTI Nanotech (WCM-Nanotech2012),
Santa Clara, CA, Jun. 2012, vol. 2, pp. 734-737.
X. Zhou, "Physics-Based Compact Variability/Reliability
Modeling for Emerging Double-Gate/Nanowire MOSFETs," (Invited Talk),
2011
IEEE International Conference on Electron Devices and Solid-State Circuits
(EDSSC2011),
Tianjin, China, Nov. 17, 2011.
X. Zhou, S. H. Lin, and M. K. Srikanth, "Statistical
Compact Modeling for Emerging Nanowire / FinFET Mismatch and Variance Studies,"
(Invited Paper), Proc. of the 6th
International Conference on Materials for Advanced Technologies (ICMAT2011),
Symposium
W: Reliability and Variability of Emerging Devices for Future Technologies
and ULSI Circuits and Systems, Singapore, June 2011, Paper
W6-2.
X. Zhou, "Xsim: A Unified Compact Model for Bulk/SOI/DG/GAA
MOSFETs," (Invited Paper), Proc.
Nanotech (WCM-Nanotech2011),
Boston, MA, Jun. 2011, vol. 2, pp. 726-731.
J. B. Zhang, X. Zhou, G. J. Zhu, and S. H. Lin, "Charge
Partition in Lateral Nonuniformly-Doped Transistor," Proc.
Nanotech (WCM-Nanotech2011),
Boston, MA, Jun. 2011, vol. 2, pp. 784-787.
S. H. Lin, X. Zhou, Z. H. Chen, M. K. Srikanth, and
J. B. Zhang, "Hot-Carrier-Induced Current Degradation in Deep Sub-Micron
MOSFETs from Subthreshold to Strong Inversion Region," Proc.
Nanotech (WCM-Nanotech2011),
Boston, MA, Jun. 2011, vol. 2, pp. 806-809.
Z. H. Chen, X. Zhou, Y. Z. Hu, and M. K. Srikanth,
"Neutral Interface Traps for Negative Bias Temperature Instability," Proc.
of the 2011 IEEE Reliability Physics Symposium (IRPS2011),
Monterey, CA, Apr. 2011, pp. 913-914.
X. Zhou, "Challenges and Trends in Unified Compact
Modeling of Conventional (Bulk/SOI) and Emerging (Multigate/Nanowire) MOSFETs,"
(Keynote), International Symposium
on Next-Generation Electronics (ISNE2010),
Kaohsiung, Taiwan, November 2010, pp. 1-2.
C. Q. Wei, Y.-Z. Xiong, X. Zhou, N. Singh, X.-J.
Yuan, G. Q. Lo, L. Chan, and D.-L. Kwong, "Comparative Study of 1/f Noise
Degradation Caused by Fowler–Nordheim Tunneling Stress in Silicon Nanowire
Transistors and FinFETs," IEEE Trans. Electron
Devices, Vol. 57, No. 10, pp.
2774-2779, October 2010.
C. Q. Wei, Y.-Z. Xiong, and X. Zhou, "Test Structure
for Characterization of Low-Frequency Noise in CMOS Technologies," IEEE
Trans. Instr. Meas., Vol. 57, No. 7, pp.
1860-1865, July 2010.
X. Zhou, G. J. Zhu, M. K. Srikanth, S. H. Lin, Z.
H. Chen, J. B. Zhang, C. Q. Wei, Y. F. Yan, R. Selvakumar, and Z. H. Wang,
"Xsim: Benchmark Tests for the Unified DG/GAA MOSFET Compact Model," Proc.
of the NSTI Nanotech 2010 (WCM-Nanotech2010),
Anaheim, CA, June 2010, Vol. 2, pp. 785-788.
G. J. Zhu, X. Zhou, Y. K. Chin, K. L. Pey, J. B.
Zhang, G. H. See, S. H. Lin, Y. F. Yan, and Z. H. Chen, "Subcircuit Compact
Model for Dopant-Segregated Schottky Gate-All-Around Si-Nanowire MOSFETs,"
IEEE
Trans. Electron Devices,
Vol.
57, No. 4, pp.
772-781, April 2010.
Z. H. Chen, X. Zhou, G. J. Zhu, and S. H. Lin, "Interface-Trap
Modeling for Silicon-Nanowire MOSFETs," Proc.
of the 2010 IEEE Reliability Physics Symposium (IRPS2010),
Anaheim, CA, May 2010, pp. 977-980.
X. Zhou, G. J. Zhu, S. H. Lin, Z. H. Chen, M. K.
Srikanth, Y. F. Yan, R. Selvakumar, W. Chandra, J. B. Zhang, C. Q. Wei,
Z. H. Wang, and P. Bathla, "Subcircuit Approach to Inventive Compact Modeling
for CMOS Variability and Reliability," Proc.
of the 12th International Symposium on Integrated Circuits, Devices &
Systems (ISIC2009),
Singapore, Dec. 2009, pp. 133-138.
X. Zhou, G. J. Zhu, S. H. Lin, C. Q. Wei, J. B. Zhang,
Z. H. Chen, M. K. Srikanth, R. Selvakumar, and Y. F. Yan, "Unification
of MOSFET Compact Models with the Unified Regional Modeling Approach,"
(Invited Talk), MOS-AK Workshop,
Baltimore, MD, Dec. 9, 2009.
Z. H. Chen, X. Zhou, G. J. Zhu, and S. H. Lin, "Surface
Recombination/Generation Velocity in Metal-Oxide-Silicon Field-Effect Transistors,"
Proc.
of the 2009 IEEE Conference on Electron Devices and Solid-State Circuits
(EDSSC2009),
Xi'an, China, Dec. 2009, paper 6.4.
Z. H. Chen, X. Zhou, and G. J. Zhu, "Effects of Translational
Layer of Gate Insulator on Recombination DC Current-Voltage Lineshape in
Metal-Oxide-Silicon Transistors," Jpn.
J. Appl. Phys., Vol. 48, No. 9, 091403,
2009.
C. Q. Wei, Y. Jiang, Y.-Z. Xiong, X. Zhou, N. Singh,
S. C. Rustagi, G. Q. Lo, and D.-L. Kwong, "Impact of Gate Electrode on
1/f Noise of Gate-All-Around Silicon Nanowire Transistors," IEEE
Electron Device Lett., Vol. 30, No. 10,
pp. 1081-1083, Oct. 2009.
G. J. Zhu, X. Zhou, Y. K. Chin, K. L. Pey, G. H.
See, S. H. Lin, and J. B. Zhang, “Subcircuit Compact Model for Dopant-Segregated
Schottky Silicon-Nanowire MOSFETs,” Proc.
of the 2009 International Conference on Solid State Devices and Materials
(SSDM2009),
Sendai, Japan, Oct. 2009, pp. 402-403.
C. Q. Wei, Y.-Z. Xiong, X. Zhou, "Investigation of
Low-Frequency Noise in N-Channel FinFETs From Weak to Strong Inversion,"
IEEE
Trans. Electron Devices, Vol. 56, No.
11, pp. 2800-2810, November 2009.
C. Q. Wei, Y.-Z. Xiong, X. Zhou, N. Singh, S. C.
Rustagi, G. Q. Lo, and D.-L. Kwong, "Investigation of Low-Frequency Noise
in Silicon Nanowire MOSFETs in the Subthreshold Region," IEEE
Electron Device Lett., Vol. 30, No. 6,
pp. 668-671, June 2009.
X. Zhou, G. J. Zhu, G. H. See, J. B. Zhang, S. H.
Lin, C. Q. Wei, Z. H. Chen, M. K. Srikanth, Y. F. Yan, R. Selvakumar, and
W. Chandra, “Unified Compact Modeling for Bulk/SOI/FinFET/SiNW MOSFETs,”
(Invited
Paper), Proc. of the 2nd International
Workshop on Electron Devices and Semiconductor Technology (IEDST2009),
Mumbai, India, June 2009, Paper
I8.
X. Zhou, G. J. Zhu, M. K. Srikanth, R. Selvakumar,
Y. F. Yan, W. Chandra, J. B. Zhang, S. H. Lin, C. Q. Wei, and Z. H. Chen,
"Compact Model Application to Statistical/Probabilistic Technology Variations,"
Proc.
of the 12th International Conference on Modeling and Simulation of Microsystems
(WCM-Nanotech2009), Houston, TX, May 2009,
Vol. 3, pp. 612-615.
G. J. Zhu, X. Zhou, G. H. See, S. H. Lin, C. Q. Wei,
and J. B. Zhang, "A Unified Compact Model for FinFET and Silicon Nanowire
MOSFETs," Proc. of the 12th International
Conference on Modeling and Simulation of Microsystems (WCM-Nanotech2009),
Houston, TX, May 2009, Vol. 3, pp. 588-591.
S. H. Lin, X. Zhou, G. H. See, G. J. Zhu, C. Q. Wei,
J. B. Zhang, and Z. H. Chen, "A Simple, Accurate Capacitance-Voltage Model
of Undoped Silicon Nanowire MOSFETs," Proc.
of the 12th International Conference on Modeling and Simulation of Microsystems
(WCM-Nanotech2009), Houston, TX, May 2009,
Vol. 3, pp. 643-646.
C. Q. Wei, Y.-Z. Xiong, and X. Zhou, "1/f Noise Model
for Double-Gate FinFET Biased in Weak Inversion," Proc.
of the 12th International Conference on Modeling and Simulation of Microsystems
(WCM-Nanotech2009), Houston, TX, May 2009,
Vol. 3, pp. 639-642.
Z. H. Chen, X. Zhou, G. H. See, Z. M. Zhu, and G.
J. Zhu, "Interface Traps in Surface-Potential-Based MOSFET Models," Proc.
of the 12th International Conference on Modeling and Simulation of Microsystems
(WCM-Nanotech2009), Houston, TX, May 2009,
Vol. 3, pp. 542-545.
X. Zhou, G. H. See, G. J. Zhu, S. H. Lin, C. Q. Wei,
nd J. B. Zhang, "Unified Regional Modeling Approach to Emerging Multiple-Gate/Nanowire
MOSFETs," (Invited Paper), Proc.
of the 9th International Conference on Solid-State and Integrated-Circuit
Technology (ICSICT2008),
Beijing, China, October 20-23, 2008, Paper B1.2.
G. J. Zhu, G. H. See, S. H. Lin, C. Q. Wei, J. B.
Zhang, Z. H. Chen, R. Selvakumar, and X. Zhou, "Xsim: Unification of MOSFET
Compact Models with the Unified Regional Modeling Approach," poster presentation
at the
MOS-AK/ESSDERC/ESSCIRC Workshop, Edinburgh,
UK, September 19, 2008.
X. Zhou, G. H. See, G. J. Zhu, Z. M. Zhu, S. H. Lin,
C. Q. Wei, A. Srinivas, and J. B. Zhang, "New Properties and New Challenges
in MOS Compact Modeling," Proc. of the
11th International Conference on Modeling and Simulation of Microsystems
(WCM-Nanotech2008),
Boston, MA, June 2-5, 2008, Vol. 3, pp. 750-755.
G. H. See, X. Zhou, G. Zhu, Z. Zhu, S. Lin, C. Wei,
J. Zhang, and A. Srinivas, "Unified Regional Surface Potential for Modeling
Common-Gate Symmetric/Asymmetric Double-Gate MOSFETs with Any Body Doping,"
Proc.
of the 11th International Conference on Modeling and Simulation of Microsystems
(WCM-Nanotech2008),
Boston, MA, June 2-5, 2008, Vol. 3, pp. 770-773.
G. H. See, X. Zhou, G. Zhu, Z. Zhu, S. Lin, C. Wei,
J. Zhang, and A. Srinivas, "Unified Regional Surface Potential for Modeling
Common-Gate Symmetric/Asymmetric Double-Gate MOSFETs with Quantum Mechanical
Correction," Proc. of the 11th International
Conference on Modeling and Simulation of Microsystems (WCM-Nanotech2008),
Boston, MA, June 2-5, 2008, Vol. 3, pp. 756-759.
G. J. Zhu, G. H. See, X. Zhou, Z. M. Zhu, S. H. Lin,
C. Q. Wei, J. B. Zhang, and A. Srinivas, "Quasi-2D Surface-Potential Solution
to Three-Terminal Undoped Symmetric Double-Gate Schottky-Barrier MOSFETs,"
Proc.
of the 11th International Conference on Modeling and Simulation of Microsystems
(WCM-Nanotech2008),
Boston, MA, June 2-5, 2008, Vol. 3, pp. 760-763.
C. Q. Wei, Y. Z. Xiong, X. Zhou, and L. Chan, "A
Technique for Constructing RTS Noise Model Based on Statistical Analysis,"
to appear in Proc. of the 11th International
Conference on Modeling and Simulation of Microsystems (WCM-Nanotech2008),
Boston, MA, June 2-5, 2008, Vol. 3, pp. 885-888.
X. Zhou, G. H. See, G. J. Zhu, Z. M. Zhu, S. H. Lin,
C. Q. Wei, A. Srinivas, and J. B. Zhang, "New Challenges in MOS Compact
Modeling for Future Generation CMOS," (Invited Paper), Proc.
of the 2008 IEEE International Nanoelectronics Conference (INEC2008),
Shanghai, China, March 24-28, 2008.
G. H. Lim, X. Zhou, K. Khu, Y. K. Yoo, F. Poh, G.
H. See, Z. M. Zhu, C. Q. Wei, S. H. Lin, and G. J. Zhu, “Physics based
scalable MOSFET mismatch model for statistical circuit simulation,” Proc.
of the 2007 IEEE Conference on Electron Devices and Solid-State Circuits
(EDSSC2007),
Tainan, December 2007, pp.
1063-1066.
G. H. Lim, X. Zhou, K. Khu, Y. K. Yoo, F. Poh, G.
H. See, Z. M. Zhu, C. Q. Wei, S. H. Lin, and G. J. Zhu, “Impact of BEOL,
multi-fingered layout design, and gate protection diode on intrinsic MOSFET
threshold voltage mismatch,” Proc. of the
2007 IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC2007),
Tainan, December 2007, pp.
1059-1062.
C. Q. Wei, X. Zhou, and G. H. See, “A New Electric-field-driven
Impact Ionization Current Model Applicable to Both Bulk and SOI MOSFETs
by Considering Self-lattice-heating,” the
2007 International Semiconductor Device Research Symposium (ISDRS2007),
College Park, MD, December 2007.
Z. Zhu, X. Zhou, S. C. Rustagi, G. H. See, S. Lin,
G. Zhu, C. Wei, and J. Zhang, "Analytic and explicit current model of undoped
double-gate MOSFETs," Electron. Lett.,
Vol. 43, No. 25, pp. 1464-1466, December 2007.
S. H. Lin, X. Zhou, G. H. See1, Z. M. Zhu, G. H.
Lim, C. Q. Wei, G. J. Zhu, Z. H., Yao, X. F. Wang, M. Yee, L. N. Zhao,
Z. F. Hou, L. K. Ang, T. S. Lee, W. Chandra, "A Rigorous Surface-Potential-Based
I-V Model for Undoped Cylindrical Nanowire MOSFETs," Proc.
of the 7th International Conference on Nanotechnology (IEEE-Nano2007),
Hong Kong, August 2-5, 2007, pp. 889-892.
X. Zhou, G. H. See, Z. M. Zhu, S. H. Lin, C. Q. Wei,
G. J. Zhu, G. H. Lim, "Unified Compact Modeling of Emerging Multiple-Gate
MOSFETs," (Invited Paper), Proc.
of the 2007 International Workshop on Electron Devices and Semiconductor
Technology (IEDST2007),
Beijing, China, June 4, 2007, pp.
31-36.
X. Zhou, G. H. See, G. J. Zhu, K. Chandrasekaran,
Z. M. Zhu, S. Rustagi, S. H. Lin, C. Q. Wei, and G. H. Lim, "Unified Compact
Model for Generic Double-Gate MOSFETs," (Invited Paper), Proc.
of the 10th International Conference on Modeling and Simulation of Microsystems
(WCM-Nanotech2007),
Santa Clara, CA, May 20-24, 2007, Vol. 3, pp. 538-543.
G. H. See, X. Zhou, K. Chandrasekaran, S. B. Chiah,
Z. Zhu, G. H. Lim, C. Q. Wei, S. H. Lin, and G. J. Zhu, "Gummel Symmetry
with Higher-order Derivatives in MOSFET Compact Models," Proc.
of the 10th International Conference on Modeling and Simulation of Microsystems
(WCM-Nanotech2007),
Santa Clara, CA, May 20-24, 2007, Vol. 3, pp. 613-616.
X. Zhou, K. Chandrasekaran, G. H. See, Z. M. Zhu,
G. H. Lim, S. H. Lin, C. Q. Wei, S. B. Chiah, M. Cheng, S. Chu, L.-C. Hsia,
and S. Rustagi, "Towards
Unification of MOS Compact Models with the Unified Regional Approach,"
(Invited Paper), Proc. of the 8th
International Conference on Solid-State and Integrated-Circuit Technology
(ICSICT2006),
Shanghai, China, Oct. 23-26, 2006, pp. 1193-1197.
W. Z. Shangguan, X. Zhou, S. B. Chiah,
G. H. See, K. Chandrasekaran, "A
Transfer-matrix Based Compact Gate Tunneling Current Model," the
3rd International Conference on Materials for Advanced Technologies (ICMAT-2005),
Symposium L: Materials Physics at Interfaces, Singapore, July 3-8, 2005,
Paper L-8-OR21.
X. Zhou, S. B. Chiah, K. Chandrasekaran,
G. H. See, W. Z. Shangguan, S. M. Pandey,
C. H. Ang, M. Cheng, and S. Chu, L.-C. Hsia,
"Unified Regional Charge Model with Non-pinned Surface Potential," (Invited
Paper), 2nd International Workshop
on Compact Modeling (IWCM-2005) at the Asia and South Pacific Design Automation
Conference (ASP-DAC2005), Shanghai, January
20, 2005.
G. H. See, S. B. Chiah, X. Zhou, K. Chandrasekaran,
W. Shangguan, S. M. Pandey, M. Cheng, S. Chu, and L.-C. Hsia, "Unified
Regional Charge-based MOSFET Model Calibration," Proc.
of the NSTI Nanotech 2005 (WCM-MSM2005),
Anaheim, CA, May 8-12, 2005, Vol. WCM, pp. 174-150.
X. Zhou, S. B. Chiah, K. Chandrasekaran, G. H. See,
W. Shangguan, S. M. Pandey, C. H. Ang, M. Cheng, S. Chu, and L.-C. Hsia,
"Unified Regional Charge
Model with Non-pinned Surface Potential," (Invited Paper), Proc.
of the 2nd International Workshop on Compact Modeling (IWCM-2005),
pp. 13-17, presented at the Asia and South
Pacific Design Automation Conference (ASP-DAC2005),
Shanghai, January 18-21, 2005.
X. Zhou and S. B. Chiah, "XSIM/DOUST: A Compact Model for Design and Optimization
of Ultra-Small Transistors," EEE Research Bulletin,
School of Electrical and Electronic Engineering, Nanyang Technological
University, January 2002, pp. 12-13.
Y. Wang, K. Y. Lim, W. Qian, and X. Zhou, "Investigation
of Reverse Short Channel Effect with Numerical and Compact Models,"
in Design, Modeling, and Simulation in Microelectronics, Bernard
Courtois, Serge N. Demidenko, L. Y. Lau, Editors,
Proc. of SPIE, Vol. 4228, pp. 366-373, 2000. Presented
at
the 2nd International Symposium on Microelectronics
and Assembly (ISMA2000),
Singapore, November 27 - December 1, 2000.
"Physics-Based Compact Variability/Reliability Modeling
for Emerging Double-Gate/Nanowire MOSFETs," (Invited Talk), 2011
IEEE International Conference on Electron Devices and Solid-State Circuits
(EDSSC2011),
Tianjin, China, Nov. 17, 2011.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," Invited Talk
(IEEE EDS Distinguished Lecture Program),
Institute
of Microelectronics, CAS, China, Nov. 15, 2011.
"Xsim: A Unified Compact Model for Bulk/SOI/DG/GAA
MOSFETs," Invited Talk,
Fudan University, Shanghai, China, Nov. 1, 2011.
"Physics-Based Compact Variability/Reliability Modeling
for Emerging Double-Gate/Nanowire MOSFETs," (Invited Talk), the
9th International Conference on ASIC (ASICON2011),
Xiamen, China, Oct. 28, 2011.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," Invited Talk
(IEEE EDS Distinguished Lecture Program),
Xiamen University, Xiamen, China, Oct. 26, 2011.
"Compact Model Application to Statistical Variability
and Reliability Studies," Invited Talk,
Tokyo Institute of Technology, Yokohama, Japan, Aug. 29, 2011.
"Statistical Compact Modeling for Emerging Nanowire
/ FinFET Mismatch and Variance Studies," (Invited Paper), the
6th International Conference on Materials for Advanced Technologies (ICMAT2011),
Symposium
W: Reliability and Variability of Emerging Devices for Future Technologies
and ULSI Circuits and Systems, Singapore, June 30, 2011.
"Xsim: A Unified Compact Model for Bulk/SOI/DG/GAA
MOSFETs," (Invited Paper), the NSTI
Nanotech 2011 (WCM-Nanotech2011),
Boston, MA, June 15, 2011.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," IEEE EDS WIMNACT-29,
National Chiao Tung University, Hsinchu, May 27, 2011.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," Invited Talk
(IEEE EDS Distinguished Lecture Program),
Rochester Institute of Technology, Rochester, May 12, 2011.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," Invited Talk,
Fudan University, Shanghia, Apr. 27, 2011.
"Neutral Interface Traps for Negative Bias Temperature
Instability," 2011 IEEE Reliability Physics
Symposium (IRPS2011),
Monterey, CA, Apr. 13, 2011.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," Invited Talk,
Hewlett-Packard, Singapore, Feb. 28, 2011.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," Invited Talk,
Institute of Microelectronics, Tsinghua University, Beijing, China, Jan.
5, 2011.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," IEEE EDS WIMNACT-26,
Tianjin University, Tianjin, China, Dec. 29, 2010.
"Challenges and Trends in Unified Compact Modeling
of Conventional (Bulk/SOI) and Emerging (Multigate/Nanowire) MOSFETs,"
(Keynote), International Symposium
on Next-Generation Electronics (ISNE2010),
Kaohsiung, Taiwan, Nov. 18, 2010.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," Invited Talk,
SMIC, China, Shanghai, Nov. 3, 2010.
"A Unified Compact Model for Emerging DG FinFETs
and GAA Nanowire MOSFETs Including Long/Short-Channel and Thin/Thick-Body
Effects," (Invited Paper), the 10th
International Conference on Solid-State and Integrated-Circuit Technology
(ICSICT2010),
Shanghai, China, Nov. 2, 2010.
"Unified Compact Model for FinFETs and Nanowire MOSFETs,"
the
10th International Conference on Solid-State and Integrated-Circuit Technology
(ICSICT2010),
Tutorial,
Shanghai, China, Nov. 1, 2010.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," IEEE EDS WIMNACT-25,
Australian National University, Canberra, Australia, July 30, 2010.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," IEEE EDS WIMNACT-25,
University of Western Australia, Perth, Australia, July 28, 2010.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," Invited Talk
(IEEE EDS Distinguished Lecture Program),
UC San Diego, June 25, 2010.
"Xsim: Benchmark Tests for the Unified DG/GAA MOSFET
Compact Model," Workshop on Compact Modeling,
NSTI Nanotech 2010 (WCM-Nanotech2010),
Anaheim, CA, June 23, 2010
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," Invited Talk
(IEEE EDS Distinguished Lecture Program),
Dalian, China, June 11, 2010.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," Invited Talk
(IEEE EDS Distinguished Lecture Program),
Chinese University of Hong Kong, May 20, 2010.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," IEEE EDS WIMNACT-23,
Heritage Institute of Technology, Kolkata, India, April 9, 2010.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," IEEE EDS WIMNACT-23,
National Institute of Technology, Silchar, India, April 8, 2010.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," IEEE EDS WIMNACT-23,
North Eastern Hill University, Shillong, India, April 5, 2010.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," IEEE EDS WIMNACT-23,
Indian Institute of Technology, Guwahati, India, April 2, 2010.
"Xsim: Unified Compact Model for Future Generation
MultiGate MOSFETs," Compact Model Council:
Multigate Compact Model Standardization,
Kyoto, Japan, Mar. 18, 2010.
"Unified Regional Modeling Approach to MOS Compact
Modeling," IEEE EDS WIMNACT-21,
Peking and Tsinghua Universities Student Branch Chapters, Beijing, January
7, 2010.
"Unified Regional Modeling Approach to MOS Compact
Modeling," Invited Talk,
Silterra Malaysia Sdn. Bhd., Malaysia, Dec. 23, 2009.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," Invited Talk
(IEEE EDS Distinguished Lecture Program),
AP/ED/MTT/SSC Penang Chapter, Penang, Malaysia, Dec. 22, 2009.
"Subcircuit Approach to Inventive Compact Modeling
for CMOS Variability and Reliability," the
12th International Symposium on Integrated Circuits, Devices & Systems
(ISIC2009),
Singapore, Dec. 15, 2009.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," Invited Talk,
Globalfoundries, Sunnyvale, CA, Dec. 10, 2009.
"Unification of MOSFET Compact Models with the Unified
Regional Modeling Approach," (Invited Talk), MOS-AK
Workshop, Baltimore, MD, Dec. 9, 2009.
"Compact Model Application to Statistical/Probabilistic
Technology Variations," Invited Talk,
2nd IITB-NTU Workshop, Indian Institute of Technology - Bombay, Mumbai,
Nov. 20, 2009.
"Mixed-Signal Multi-Level Circuit Simulation: An
Implicit Mixed-Mode Solution," Research
Seminar, Technical University of Munich,
Germany, Oct. 13, 2009.
"Compact Model Application to Statistical/Probabilistic
Technology Variations," Invited Talk,
Technical University of Munich, Germany, Oct. 13, 2009.
"Unified Multi-Level Modeling for Future CMOS Technology
Generations," Research Seminar,
Technical University of Munich, Germany, Oct. 12, 2009.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," Invited Talk
(IEEE EDS Distinguished Lecture Program),
Xidian University, Xi'an, Sep. 1, 2009.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," Invited Talk
(IEEE EDS Distinguished Lecture Program),
University of Electronic Science and Technology of China, Chengdu, Aug.
24, 2009.
"Compact Model Application to Statistical and Probabilistic
Technology Variations," Invited Talk,
Workshop on Sustainable Nanoelectronics and Information Technology, Rice
Univ., Houston, TX, June 24, 2009.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," IEEE EDS WIMNACT-19,
Bangladesh, June 6, 2009.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," IEEE EDS WIMNACT-18,
Mysore, June 4, 2009.
"Unification of MOS Compact Models with the Unified
Regional Modeling Approach," IEEE EDS WIMNACT-18,
Bangalore, June 3, 2009.
"Unified Compact Modeling for Bulk/SOI/FinFET/SiNW
MOSFETs," (Invited Paper), the 2nd
International Workshop on Electron Devices and Semiconductor Technology
(IEDST2009),
Mumbai, India, June 2, 2009.
"Compact Model Application to Statistical/Probabilistic
Technology Variations," the 12th International
Conference on Modeling and Simulation of Microsystems (WCM-Nanotech2009),
Houston, TX, May 6, 2009.
"MOSFET Comact Modeling: History, Essentials, Challenges,
and Outlook," Special Technical Seminar,
Mediateck Singapore Pte Ltd, Apr. 9, 2009.
"Unified Regional Modeling Approach to Emerging Multiple-Gate/Nanowire
MOSFETs," (Invited Paper), the 9th
International Conference on Solid-State and Integrated-Circuit Technology
(ICSICT2008),
Beijing, China, October 21, 2008.
"Unified Compact Modeling of Emerging Multiple-Gate
MOSFETs," Invited Talk (IEEE EDS Distinguished
Lecture Mini-colloquium), CIE-YC'2008, Guangzhou,
China, September 24, 2008.
"New Properties and New Challenges in MOS Compact
Modeling," Workshop on Compact Modeling,
NSTI Nanotech 2008 (WCM-Nanotech2008),
Boston, MA, June 3, 2008.
"Unified Compact Modeling of Emerging Multiple-Gate
MOSFETs," Invited Talk (IEEE EDS Distinguished
Lecture Mini-colloquium), 15th Workshop and IEEE EDS Mini-colloquium
on NAnometer CMOS Technology (WIMNACT-HZ), Hangzhou,
China, March 28, 2008.
"New Challenges in MOS Compact Modeling for Future
Generation CMOS," Invited Talk,
Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, Switzerland,
March 11, 2008.
"New Challenges in MOS Compact Modeling for Future
Generation CMOS," Invited Talk,
University of Rochester, NY, December 19, 2007.
"Unified Compact Modeling of Emerging Multiple-Gate
MOSFETs," Invited Talk (IEEE EDS Distinguished
Lecture Mini-colloquium), 13th Workshop and IEEE EDS Mini-colloquium
on NAnometer CMOS Technology (WIMNACT-HK/Singapore),
Singapore, July 25, 2007.
"Unified Compact Modeling of Emerging Multiple-Gate
MOSFETs," Invited Talk (IEEE EDS Distinguished
Lecture Mini-colloquium), 13th Workshop and IEEE EDS Mini-colloquium
on NAnometer CMOS Technology (WIMNACT-HK/Singapore),
Hong Kong, July 23, 2007.
"Unified Compact Modeling of Emerging Multiple-Gate
MOSFETs," (Invited Paper), the 2007
International Workshop on Electron Devices and Semiconductor Technology
(IEDST2007),
Beijing, China, June 4, 2007.
"Unified Compact Model for Generic Double-Gate MOSFETs,"
(Invited Paper), Workshop on Compact
Modeling, NSTI Nanotech 2007 (WCM-Nanotech2007),
Santa Clara, CA, May 22, 2007.
"Compact Modeling: Computational Investigation of Novel Device Structures
and Concepts using TCAD," Invited Short Course,
Faculty of Electrical Engineering, Universiti Teknologi Malaysia, Malaysia,
May 18, 2007.
"Compact Modeling: Parameter Extraction and Circuit Simulation," Invited
Short Course, Faculty of Electrical Engineering, Universiti
Teknologi Malaysia, Malaysia, May 17, 2007.
"Compact Modeling: Formulation and Characterization," Invited
Short Course, Faculty of Electrical Engineering, Universiti
Teknologi Malaysia, Malaysia, May 16, 2007.
"Compact Modeling: Overview, Introduction and Basic Concepts," Invited
Short Course, Faculty of Electrical Engineering, Universiti
Teknologi Malaysia, Malaysia, May 15, 2007.
"Towards Unification of MOS Compact Models with the
Unified Regional Approach," (Invited Paper), the
8th International Conference on Solid-State and Integrated-Circuit Technology
(ICSICT2006),
Shanghai, China, Oct. 24, 2006.
"Unified Regional Approach to MOS Transistor Compact Modeling for Circuit
Simulation," Invited Talk, Altera Corp.,
San Jose, CA, August 11, 2006.
"Towards Unification of MOSFET Compact Models with the Unified Regional
Approach," Invited Talk, Advanced Micro
Devices, Sunnyvale, CA, August 11, 2006.
"Towards Unification of MOSFET Compact Models with the Unified Regional
Approach," Invited Talk, Cadence Design
Systems, San Jose, CA, August 9, 2006.
"Technology-Based Predictive Compact Model Development for Next Generation
CMOS," SRC Annual Review Presentation, Durham, NC, USA, June 29,
2004.
"Technology-Based Predictive Compact Model Development for Next Generation
CMOS," Faculty Presentation - SRC Project Review, Chartered Semiconductor
Manufacturing, Singapore, April 27, 2004.
"Unified Regional Approach to Consistent and Symmetric
DC/AC Modeling of Deep-Submicron MOSFETs," CNEG
lunch-time seminar series, Nanyang Technological University,
February 28, 2004.
"The
Missing Link to Seamless Simulation,"
Invited
Talk (IEEE EDS Distinguished Lecture Mini-colloquium), 3rd Workshop
and IEEE EDS Mini-colloquium on NAnometer CMOS Technology (WIMNACT-Singapore),
Singapore, October 15, 2003.
"Multi-Level
Modeling of Deep-Submicron CMOS ULSI Systems," Invited
Talk (IEEE EDS Distinguished Lecturer Program), Microelectronics
R&D Center, Chinese Academy of Sciences, Beijing, December 13, 2002;
Institute of Microelectronics, Tsinghua University, Beijing, December 13,
2002.
"MOSFET Compact I-V Modeling for Deep-Submicron Technology
Development,"
Invited Talk, Swiss Federal
Institute of Technology - Lausanne (EPFL), Lausanne, Switzerland, June
17, 2002.
"MOSFET Compact I-V Modeling for Deep-Submicron Technology
Development,"
Invited Talk, Advanced
Micro Devices, Inc., Sunnyvale, CA, April 16, 2002; Intel Corp., Santa
Clara, CA, April 17, 2002; LSI Logic Corp., Santa Clara, CA, April 18,
2002.
"MOSFET Compact I-V Modeling for Deep-Submicron Technology
Development,"
Invited Talk, Center
for Integrated Systems, Stanford University, March 2, 2001; Electrical
Engineering Department, University of California at Berkeley, March 22,
2001; LSI Logic Corp., Santa Clara, CA, March 26, 2001.
"Unified MOSFET Compact Model Formulation for Deep-Submicron Technology
Development and Multi-Level Circuit Simulation," Invited
Talk, Maxim Integrated Products, Inc., Sunnyvale, CA, March
23, 2000; LSI Logic Corp., Santa Clara, CA, March 24, 2000.
"Unified MOSFET Compact Model Formulation Through Physics-Based Effective
Transformation for Multi-Level Technology Modeling and Circuit Design,"
Research
Seminar, McMaster University, Canada, December 13, 1999; LSI
Logic Corp., Fairport, NY, December 16, 1999; Eastman Kodak Co., Rochester,
NY, December 17, 1999; Department of Electrical and Computer Engineering,
University of Rochester, NY, December 17, 1999.
"A Novel Approach to Compact I-V Modeling for Deep-Submicron
MOSFET's Technology Development," Invited Talk,
Intel Corp., Santa Clara, CA, April 23, 1999.
"Compact Threshold Voltage Modeling for Deep-Submicron MOSFET's Based on
Numerical Simulation, Empirical Formulation, and Experimental Correlation,"
Invited
Talk, Advanced Micro Devices, Inc., Sunnyvale, CA, June 11,
1998; Avant! Corp., Fremont, CA, June 12, 1998; Motorola, Inc., Austin,
TX, June 15, 1998; Texas Instruments, Inc., Dallas, TX, June 18, 1998.
"Unified Compact Model for FinFETs and Nanowire MOSFETs,"
the
10th International Conference on Solid-State and Integrated-Circuit Technology
(ICSICT2010),
Tutorial,
Shanghai, China, Nov. 1, 2010.
"Introduction to MOS Transistor Compact Modeling for Technology Development,
Device Design, and Circuit Simulation," 5-day in-house training course,
Altera Corp. (M) Sdn. Bhd., Malaysia, August 23-27, 2010.
"Introduction to MOS Transistor Compact Modeling for SPICE Circuit Simulation,"
in-house
short course, Systems on Silicon Manufactoring Co. Pte. Ltd.
(SSMC), Singapore, June 22, 2007.
"Introduction to MOS Transistor Compact Modeling for SPICE Circuit Simulation,"
in-house
short course, United Microelectronics Corporation (UMCi), Singapore,
June 22, 2006.
"Introduction to MOS Transistor Compact Modeling for SPICE Circuit Simulation,"
in-house
short course, United Microelectronics Corporation (UMCi), Singapore,
November 11, 2005.
"Introduction to MOS Transistor Compact Modeling for SPICE Circuit Simulation,"
in-house
short course, Systems on Silicon Manufactoring Co. Pte. Ltd.
(SSMC), Singapore, November 7, 2005.