Design and Optimization of Ultra-Small Transistors (DOUST)

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Project DOUST: Design and Optimization of Ultra-Small Transistors


Initiating rather than following trend. (Bill Gates)


"Everything should be made as simple as possible, but not any simpler." (Elbert Einstein)

"Politics is for the present, but an equation is something for eternity." (Elbert Einstein)

"The best way to predict future is to invent it." (Alan Kay)

"The sciences do not try to explain, they hardly even try to interpret, they mainly make models.  By a model is meant a mathematical construct which, with the addition of certain verbal interpretations, describes observed phenomena.  The justification of such a mathematical construct is solely and precisely that it is expected to work." (John von Neumann)


This project is directed towards the construction and implementation of a framework for the design and optimization of ultra-small transistors in the context of the 0.18-µm CMOS process technology to be developed by Chartered Semiconductor Manufacturing Ltd (CSM). Sequence and segmentation of a design allows device design problems to be tackled individually and optimization to be linked with process and circuit considerations. Under this framework, transistor structures can be designed and optimized in relation to circuit constraints and fabrication parameters. Eventually, this approach will not only efficiently balance the trade-off and ensure convergence to a good design, but also make sure that resources and time are well deployed. The TCAD (technology CAD) approach to technology development, sometimes referred to as "virtual wafer fab," has been employed in all major semiconductor companies worldwide. With this approach, trade-off in determining process windows can be made for various circuit constraints and device optimization considerations without going through the expensive wafer processing.


  1. A framework for the TCAD approach to technology development and transistor design will be constructed, from which any new process/device design can be evaluated efficiently.
  2. Process and device simulators will be calibrated so that major physical models and the associated parameters can fit experimental results of a given 0.25-µm process, which will be used as a basis for the 0.18-µm technology development.
  3. Key design parameters will be identified and related to process conditions using Design of Experiments (DOE), from which process windows can be obtained to bracket the final optimal design.
  4. Simplified analytic equations will be formulated to give a first-order approximation for device performance prediction and optimization.
  5. Circuit parameters will be extracted from "virtual wafer" experiments, and compared with real experiments through SPICE simulation.
  6. Specific process and device phenomena will be investigated based on the advanced physical models and, if necessary, new models will be developed.
  7. Professional scientists and engineers as well as graduate students will be trained in this project.