Unified Approach to Bulk/SOI/UTB/s-DG MOSFET Compact Modeling
Xing Zhou*, Karthik Chandrasekaran*, Siau Ben Chiah*,**, Wangzuo Shangguan*, Zhaomin Zhu*, Guan Huei See*, Shesh Mani Pandey**, Guan Hui Lim*, Subhash Rustagi***, Michael Cheng**, Sanford Chu**, and Liang-Choo Hsia**

* School of Electrical & Electronic Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798
Phone: (65) 6790-4532.  Fax: (65) 6793-3318. Email: exzhou@ntu.edu.sg
** Chartered Semiconductor Manufacturing Ltd, 60 Woodlands Industrial Park D, St. 2, Singapore 738406
***Institute of Microelectronics, 11, Science Park Road, Singapore Science Park II, Singapore 117685

Proc. of the NSTI Nanotech 2006 (WCM-MSM2006)

Boston, MA, May 7-11, 2006, vol. 3, pp. 652-657.

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In this paper, we extend our unified regional approach to bulk-MOS charge modeling with non-pinned surface potential for various device structures, such as partially-depleted (PD) or fully-depleted (FD) ultra-thin body (UTB) silicon-on-insulator (SOI) as well as symmetric/asymmetric double-gate (s-DG/a-DG) MOSFETs.  The regional solutions make it easy to handle different device structures with explicit asymptotically physical solutions, and the unified solution combines the best features in different modeling approaches, such as surface-potential/inversion-charge/threshold-voltage based models, without the need to solve exactly at flat-band voltage.  We show that it is viable to obtain a unified solution scalable with layer thickness and doping in all regions (accumulation, depletion, weak/volume/strong inversions).  In particular, the effect of doping (even unintentional) in DG MOSFETs is studied with the regional approach.  The ultimate goal is to have one generic and scalable model with selectable accuracy and seamless transition across device types and operations.