* School of Electrical & Electronic Engineering, Nanyang Technological
University, Nanyang Avenue, Singapore 639798
Phone: (65) 6790-4532. Fax: (65) 6791-2687. Email: firstname.lastname@example.org
** Chartered Semiconductor Manufacturing Ltd, 60 Woodlands Industrial Park D, St. 2, Singapore 738406
Proc. of the NSTI Nanotech 2005 (WCM-MSM2005)
Anaheim, CA, May 8-12, 2005, WCM, pp. 147-150
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This paper presents a methodology to extract device physical parameters, i.e., gate oxide thickness (tox), channel doping (Nch), and poly-gate doping (Ngate), as well as smoothing parameters in our unified regional charge-based model using only one gate capacitance (Cgg) data. The smoothing parameters are fitted to satisfy charge neutrality at flat-band (Vfb) condition as well as continuity across regions of operation near flat-band and threshold voltage (Vt), including higher-order derivatives. Through a one-iteration calibration approach, our unified regional charge-based model can predict accurately the experimental Cgg data from a 0.11-um CMOS technology. Compared with iterative/explicit surface-potential-based models, which often require optimization techniques such as genetic algorithm due to parameter correlation, our unified regional approach has the advantage of less parameter dependency since physical parameters are uncorrelated to the smoothing parameters.