* School of Electrical & Electronic Engineering, Nanyang Technological
University, Nanyang Avenue, Singapore 639798
Phone: (65) 6790-4532. Fax: (65) 6791-2687. Email: firstname.lastname@example.org
** Chartered Semiconductor Manufacturing Ltd, 60 Woodlands Industrial Park D, St. 2, Singapore 738406
Proc. of the NSTI Nanotech 2005 (WCM-MSM2005)
Anaheim, CA, May 8-12, 2005, WCM, pp. 143-146.
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This paper presents the calibration methodology for our unified length/width-dependent MOSFET drain-current (Ids) model with length/width-dependent threshold-voltage (Vt) model in the entire geometry/bias range based on a 0.11-um CMOS technology. The model has been formulated with built-in physical effects to account for electrical characteristics of fabricated short-channel/narrow-width devices while maintaining Gummel symmetry. Through a one-iteration parameter extraction using minimum measurement data, the model can predict accurately and physically the experimental I V data, including output conductance, transconductance, and their derivatives.