Compact Model for Manufacturing Design and Fluctuation Study

Khee Yong Lim* and Xing Zhou†

* Chartered Semiconductor Manufacturing Ltd, 60 Woodlands Industrial Park D, St. 2, Singapore 738406
Phone: 65-3946251. Fax: 65-3946505. Email:
† School of Electrical & Electronic Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798

Proc. of the 5th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2002)

San Juan, Puerto Rico, April 22-25, 2002, pp. 746-749.

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In this article, a physics based compact model [1, 2] has been used as a tool for manufacturing process variability study. Three critical end-of-line (EOL) measured electrical testing (ET) parameters, namely Vth, Ion and Ioff, of a 0.25µm CMOS technology together with three in-line device parameters (tox, Leff, Ns) are used for the study. Based on the compact model, the sensitivity of each EOL parameter with respect to individual in-line device parameter can be easily computed. To systematically examine the correlation of final electrical parameters with the fluctuation of in-line device parameter directly related to process, a mathematical model that expresses ET parameter variance in terms of process-related parameter variance [3] has been employed. By combining the above mathematical model and sensitivity rate calculated from calibrated compact model together with computed normalized variance from actual experimental data, the device parameter fluctuation can be derived from measured ET fluctuation.