Siau Ben Chiah*, Xing Zhou*, Khee Yong Lim†, Alex See†, and Lap Chan†
* School of Electrical & Electronic Engineering, Nanyang Technological
University, Nanyang Avenue, Singapore 639798
Phone: (65) 790-4532. Fax: (65) 791-2687. Email: email@example.com
† Chartered Semiconductor Manufacturing Ltd, 60 Woodlands Industrial Park D, St. 2, Singapore 738406
Proc. of the 5th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2002)
San Juan, Puerto Rico, April 22-25, 2002, pp. 750-753.
Copyright | Abstract | References | Figures | Reprint | Slides | Back
© 2002 Computational Publications. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from Computational Publications.
This paper demonstrates a physically-based approach to parameter extraction of the compact Ids model we have developed for deep-submicron technology development. A two-iteration parameter-extraction scheme is described, which improves the previous one-iteration approach. Parameter calibration for the Vt model is revisited. Comparison of parabolic and linear body-bias dependency with new calibration sequence for the Vt model is carried out, which shows higher accuracy in Vt modeling for the new parabolic interpolation. Optimization for the halo pile-up centriod, LDD lateral diffusion as well as saturation velocity is carried out to improve the overall Vt and Ids modeling. This has been verified with the experimental data from a 0.18-µm CMOS technology wafer.