K. Y. Lim*, X. Zhou*‡, D. Lim†, Y. Zu†, H. M. Ho†, K. Loiko†, C. K. Lau†, M. S. Tse*, and S. C. Choo*
*School of Electrical & Electronic Engineering,
Nanyang Technological University, Nanyang Avenue, Singapore 639798
(‡Phone: 65-7991368, Fax: 65-7912687, Email: firstname.lastname@example.org)
†Chartered Semiconductor Manufacturing Ltd., 60 Woodlands Industrial Park D, Street 2, Singapore 738406
1998 IEEE Hong Kong Electron Devices Meeting (HKEDM98)
Hong Kong, August 29, 1998, pp. 114-117.
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A compact threshold voltage model is developed for the prediction of deep-submicron MOSFET’s scaling characteristic based on comprehensive 2-D device simulation, empirical formulation, and correlation to experimental data. The model incorporates the nonuniformities and nonlinearities from 2-D device physics, relates to process variables, and yet is efficient to use.