A Physically-Based Semi-Empirical Series Resistance Model for Deep-Submicron MOSFET I-V Modeling

Khee Yong Lim, Student Member, IEEE and Xing Zhou, Senior Member, IEEE

IEEE Transactions on Electron Devices, Vol. 47, No. 6, June 2000, pp. 1300-1302.

(Manuscript received August 26, 1999; revised January 31, 2000.)

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A physically-based series resistance model for deep-submicron MOSFET is presented, which includes a bias-dependent (intrinsic) component and a bias-independent (extrinsic) component.  The model is semi-empirical and consists of two physics-based fitting parameters to be extracted with a single measurement, which can be extended to all gate-length and bias conditions.  The model can be applied to drain-current prediction and optimization due to process fluctuations such as LDD junction depth and spacer thickness.



  1. [11] X. Zhou and K. Y. Lim, "Unified MOSFET compact I-V model formulation through physics-based effective transformation," IEEE Trans. Electron Devices, Vol. 48, No. 5, pp. 887-896, May 2001.
  2. [3] Y. Wang, X. Zhou, K. Y. Lim, and S. B. Chiah, "Investigation of MOSFET series resistance by numerical simulation and compact modeling," Proc. 9th International Symposium on Integrated Circuits, Devices & Systems (ISIC2001), Singapore, Sept. 2001, pp. 238-241.
  3. [10] X. Zhou, S. B. Chiah, K. Y. Lim, Y. Wang, X. Yu, S. Chwa, A. See, and L. Chan, "Technology-dependent modeling of deep-submicron MOSFET's and ULSI circuits," (Invited Paper), Proc. 6th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT-2001), Shanghai, Oct. 2001, Vol. 2, pp. 855-860.
  4. S. K. Manhas, M. M. De Souza, A. S. Oates, "Quantifying the nature of hot carrier degradation in the spacer region of LDD MOSFETs," IEEE Trans. Device and Materials Reliability, Vol. 1, No. 3, pp. 134-143, Sept. 2001. Download PDF
  5. [15] K. Y. Lim and X. Zhou, "An analytical effective channel-length modulation model for velocity overshoot in submicron MOSFETs based on energy-balance formulation," Microelectronics Reliability, Vol. 42, No. 12, pp. 1857-1864, Dec. 2002.
  6. [10] S. B. Chiah, X. Zhou, and K. Y. Lim, "Unified Length-/Width-Dependent Drain Current Model for Deep-Submicron MOSFETs," Proc. of the 6th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2003), San Francisco, CA, Feb. 2003, vol. 2, pp. 342-345.
  7. [8] S. K. Manhas, D. Chandra Sehkar, A. S. Oates, and M. M. De Souza, "Characterisation of series resistance degradation through charge pumping technique," Microelectronics Reliability, Vol. 43, No. 4, pp. 617-624, Apr. 2004. Download PDF
  8. [6] D. M. Kim, H. C. Kimb, and H. T. Kim, "Modeling and extraction of gate bias-dependent parasitic source and drain resistances in MOSFETs," Solid-State Electron., Vol. 47, No. 10, pp. 1707-1712, Oct. 2003. Download PDF
  9. [12] C. L. Yu, L. A. Yang, and Y. Hao, "A compact I-V model for lightly-doped-drain MOSFETs," Chinese Phys. vol. 13, no. 7, pp. 1104-1109, Jul. 2004.
  10. [9] H. Katto, "A compact and accurate MOSFET model with simple expressions for linear, saturation and sub-threshold regions," Solid-State Electron., Vol. 50, No. 3, pp. 301-308, Mar. 2006. Download PDF
  11. [] A. A. Frantsuzov, N. I. Boyarkina, and V. P. Popov, "Decrease in effective electron mobility in the channel of a metal-oxide-semiconductor transistor as the gate length is decreased," Semiconductors, Vol. 42, No. 2, pp. 215-219, Feb. 2008.
  12. [] J. Kim, J. Lee, I. Song, Y. Yun, J. D. Lee, B. G. Park, H. Shin, "Accurate Extraction of Effective Channel Length and Source/Drain Series Resistance in Ultrashort-Channel MOSFETs by Iteration Method," IEEE Trans. Electron Devices, vol. 55, no. 10, pp. 2779-2784, Oct. 2008.

ISI Citation