A Physically-Based Semi-Empirical Series Resistance
Model for Deep-Submicron MOSFET I-V Modeling
Khee Yong Lim, Student Member, IEEE and Xing Zhou,
IEEE Transactions on Electron Devices,
Vol. 47, No. 6, June 2000, pp. 1300-1302.
(Manuscript received August 26, 1999; revised January 31, 2000.)
Copyright | Abstract
| References | Citation | Figures
© 2000 IEEE. Personal use of this material is permitted. However,
permission to reprint/republish this material for advertising or promotional
purposes or for creating new collective works for resale or redistribution
to servers or lists, or to reuse any copyrighted component of this work
in other works must be obtained from the IEEE.
A physically-based series resistance model for deep-submicron MOSFET
is presented, which includes a bias-dependent (intrinsic) component and
a bias-independent (extrinsic) component. The model is semi-empirical
and consists of two physics-based fitting parameters to be extracted with
a single measurement, which can be extended to all gate-length and bias
conditions. The model can be applied to drain-current prediction
and optimization due to process fluctuations such as LDD junction depth
and spacer thickness.
 K. Terada and H. Muta, “A new method to determine effective MOSFET
channel length,” Jpn. J. Appl. Phys., vol. 18, p. 935, 1979.
 G. J. Hu, C. Chang, and Y.-T. Chia, “Gate-voltage-dependent effective
channel length and series resistance of LDD MOSFET’s,” IEEE Trans. Electron
Devices, vol. 34, pp. 2469–2475, Dec. 1987.
 S. S.-S. Chung and J.-S. Lee, “A new approach to determine the drain-and-source
series resistance of LDD MOSFET’s,” IEEE Trans. Electron Devices, vol.
40, pp. 1709–1711, Sept. 1993.
 D. Esseni, H. Iwai, M. Saito, and B. Ricco, “Nonscaling of MOSFET’s
linear resistance in the deep submicrometer regime,” IEEE Electron Devices
Lett., vol. 19, pp. 131–133, Apr. 1998.
 Y. Taur et al., “A new ‘Shift and Ratio’ method for MOSFET channel-length
extraction,” IEEE Electron Devices Lett., vol. 13, pp. 267–269, May 1992.
 J.-C. Guo, S. S.-S. Chung, and C. C.-H. Hsu, “A new approach to determine
the effective channel length and the drain-and-source series resistance
of miniaturized MOSFET’s,” IEEE Trans. Electron Devices, vol. 41, pp. 1811–1818,
 C.-L. Lou, W.-K. Chim, D. S.-H. Chan, and Y. Pan, “A novel single-device
DC method for extraction of the effective mobility and source-drain resistances
of fresh and hot-carrier degraded drain-engineered MOSFET’s,” IEEE Trans.
Electron Devices, vol. 45, pp. 1317–1323, June 1998.
 K. K. Ng and W. T. Lynch, “Analysis of the gate-voltage-dependent series
resistance of MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-33, pp.
965–972, July 1986.
 E. Gondor, P. Klein, F. Schuler, and O. Kowarik, “A non-linear description
of the bias dependent parasitic resistances of quarter micron MOSFETs,”
in Proc. IEEE ICSE, Nov. 1998, pp. 97–99.
 X. Zhou, K. Y. Lim, and D. Lim, “A general approach to compact threshold
voltage formulation based on 2-D numerical simulation and experimental
correlation for deep-submicron ULSI technology development,” IEEE Trans.
Electron Devices, vol. 47, pp. 214–221, Jan. 2000.
 K. Y. Lim, X. Zhou, and D. Lim, “A predictive length-dependent saturation
current model based on accurate threshold voltage modeling,” in Proc. MSM99,
Apr. 1999, pp. 423–426.
 K. Y. Lim and X. Zhou, “A physically-based semi-empirical effective
mobility model for MOSFET compact I-V modeling,” submitted for publication.
 X. Zhou and K. Y. Lim, “A novel approach to compact I-V modeling for
deep-submicron MOSFET's technology development with process correlation,”
in Proc. MSM2000, Mar. 2000, pp. 333–336.
 —, “Unified MOSFET compact model formulation through physics-based
effective transformation,” submitted for publication.
 Y. P. Tsividis, Operation and Modeling of the MOS Transistor, NY:
McGraw-Hill, 1987, p. 128.
 X. Zhou and K. Y. Lim, “A compact MOSFET Ids model for channel-length
modulation including velocity overshoot,” in Proc. ISDRS, Dec. 1999, pp.
 X. Zhou and K. Y. Lim, "A
compact MOSFET Ids model for channel-length modulation including velocity
overshoot," Proc. 1999 International Semiconductor Device Research Symposium
(ISDRS-99), Charlottesville, VA, Dec. 1999, pp. 423-426.
 X. Zhou and K. Y. Lim, "Unified
MOSFET compact I-V model formulation through physics-based effective transformation,"
IEEE Trans. Electron Devices, Vol. 48, No. 5, pp. 887-896, May 2001.
 Y. Wang, X. Zhou, K. Y. Lim,
and S. B. Chiah, "Investigation of MOSFET series resistance by numerical
simulation and compact modeling," Proc. 9th International Symposium on
Integrated Circuits, Devices & Systems (ISIC2001), Singapore, Sept.
2001, pp. 238-241.
 X. Zhou, S. B. Chiah, K.
Y. Lim, Y. Wang, X. Yu, S. Chwa, A. See, and L. Chan, "Technology-dependent
modeling of deep-submicron MOSFET's and ULSI circuits," (Invited Paper),
Proc. 6th International Conference on Solid-State and Integrated-Circuit
Technology (ICSICT-2001), Shanghai, Oct. 2001, Vol. 2, pp. 855-860.
K. Manhas, M. M. De Souza, A. S. Oates, "Quantifying the nature
of hot carrier degradation in the spacer region of LDD MOSFETs," IEEE Trans.
Device and Materials Reliability, Vol. 1, No. 3, pp. 134-143, Sept. 2001.
 K. Y. Lim and X. Zhou, "An analytical
effective channel-length modulation model for velocity overshoot in submicron
MOSFETs based on energy-balance formulation," Microelectronics Reliability,
42, No. 12, pp. 1857-1864, Dec. 2002.
 S. B. Chiah, X.
Zhou, and K. Y. Lim, "Unified Length-/Width-Dependent Drain Current
Model for Deep-Submicron MOSFETs," Proc. of the 6th International Conference
on Modeling and Simulation of Microsystems (WCM-MSM2003), San Francisco,
CA, Feb. 2003, vol. 2, pp. 342-345.
K. Manhas, D. Chandra Sehkar, A. S. Oates, and M. M. De Souza,
"Characterisation of series resistance degradation through charge pumping
technique," Microelectronics Reliability, Vol. 43, No. 4, pp. 617-624,
M. Kim, H. C. Kimb, and H. T. Kim, "Modeling and extraction of
gate bias-dependent parasitic source and drain resistances in MOSFETs,"
Solid-State Electron., Vol. 47, No. 10, pp. 1707-1712, Oct. 2003.
L. Yu, L. A. Yang, and Y. Hao, "A compact I-V model for lightly-doped-drain
MOSFETs," Chinese Phys. vol. 13, no. 7, pp. 1104-1109, Jul. 2004.
Katto, "A compact and accurate MOSFET model
with simple expressions for linear, saturation and sub-threshold regions,"
Solid-State Electron., Vol. 50, No. 3, pp. 301-308, Mar. 2006.
 A. A. Frantsuzov, N. I. Boyarkina, and V. P.
Popov, "Decrease in effective electron mobility in the channel of a
metal-oxide-semiconductor transistor as the gate length is decreased,"
Semiconductors, Vol. 42, No. 2, pp. 215-219, Feb. 2008.
 J. Kim, J. Lee, I. Song, Y. Yun, J. D. Lee,
B. G. Park, H. Shin, "Accurate Extraction of Effective Channel Length
and Source/Drain Series Resistance in Ultrashort-Channel MOSFETs by Iteration
Method," IEEE Trans. Electron Devices, vol. 55, no. 10, pp. 2779-2784,