for Generic Undoped MOSFETs with Two Gates
W. Z. Shangguan, Xing Zhou,
Member, IEEE, Karthik Chandrasekaran, Zhaomin Zhu, Subhash C. Rustagi,
Member, Siau Ben Chiah, Guan Huei See
IEEE Transactions on Electron Devices,
54, No. 1, pp.
169-172, Jan. 2007
(Manuscript received May 19, 2006; revised
September 14, 2006.)
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We present a rigorously derived analytical Poisson solution for undoped
semiconductors and apply the general solution to the generic MOSFETs with
two gates, unifying different types such as silicon-on-insulator (SOI),
symmetric and asymmetric double gate (s-DG, a-DG) structures. The
Newton-Raphson (NR) method is used to solve the surface-potential equations
resulting from the application of the boundary conditions to the general
Poisson solution, with an initial guess very close to the exact solution.
The universal initial guess can be used as an approximate explicit solution
for fast evaluation while the iterative solution for benchmark tests.
The results demonstrate unification of surface-potential solutions
having an accuracy of 10-15 V for SOI, a-DG, and s-DG MOSFETs,
achieved with 2 to 6 iterations., Furthermore, the explicit solution yields
less than 3.5% error for back-to-front gate oxide thickness ratios larger
 H. R. Farrah and R. F. Steinberg, “Analysis of double-gate thin-film
transistor,” IEEE Trans. Electron Devices, vol. ED-14, no. 2, pp. 69–74,
 F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa,
“Double-gate silicon-on-insulator transistor with volume inversion: A new
device with greatly enhanced performance,” IEEE Electron Device Lett.,
vol. EDL-8, no. 9, pp. 410–412, Sept. 1987.
 K. K. Young, “Analysis of conduction in fully depleted SOI MOSFET’s,”
IEEE Trans. Electron Devices, vol. 36, no. 3, pp. 504–506, Mar. 1989.
 K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, “Scaling
theory for double-gate SOI MOSFET’s,” Electron Devices, IEEE Transactions
on, vol. 40, no. 12, pp. 2326–2329, Dec. 1993.
 P. Francis, A. Terao, D. Flandre, and F. Van de Wiele, “Modeling of
ultrathin double-gate nMOS/SOI transistors,” IEEE Trans. Electron Devices,
vol. 41, no. 5, pp. 715–720, May 1994.
 J. W. Sleight and R. Rios, “A continuous compact MOSFET model for fully-
and partially-depleted SOI devices,” IEEE Trans. Electron Devices, vol.
45, no. 4, pp. 821–825, Apr. 1998.
 Y. Taur, “Analytic solutions of charge and capacitance in symmetric
and asymmetric double-gate MOSFETs,” IEEE Trans. Electron Devices, vol.
48, no. 12, pp. 2861–2869, Dec. 2001.
 H. Lu and Y. Taur, “An analytic potential model for symmetric and asymmetric
DG MOSFETs,” IEEE Electron Device Lett., vol. 53, no. 5, pp. 1161–1168,
 X. Shi and M. Wong, “Analytical solutions to the one-dimensional oxide-silicon-oxide
system,” IEEE Trans. Electron Devices, vol. 50, no. 8, pp. 1793–1800, Aug.
 A. Ortiz-Conde, and F. J. Garcia-Sanchez, and S. Malobabic, “Analytic
solution of the channel potential in undoped symmetric dual-gate MOSFETs,”
IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1669–1672, Jul. 2005.
 Y. S. Yu, S. H. Kim, S. W. Hwang, and D. Ahn, “All-analytic surface
potential model for SOI MOSFETs,” IEE Proc.-Circuits Devices Systems, vol.
152, no. 2, pp. 183–188, 2005.
 A. Ortiz-Conde, R. Herrera, P. E. Schmidt, F. J. Garcia Sanchez, and
J. Andrian, “Long-channel silicon-on-insulator MOSFET theory,” Solid-State
Electron., vol. 35, pp. 1291–1298, Sept. 1992.
 A. Ortiz-Conde, F. J. Garcia Sanchez, and M. Guzman, “Exact analytical
solution of channel surface potential as an explicit function of gate voltage
in undoped-body MOSFETs using the Lambert W function and a threshold voltage
definition therefrom,” Solid-State Electron., vol. 47, pp. 2067–2074, Nov.
 K. Chandrasekaran, Z. M. Zhu, X. Zhou, W. Z. Shangguan, G. H. See,
S. B. Chiah, S. C. Rustagi, and N. Singh, “Compact Modeling of Doped Symmetric
DG MOSFETs with Regional Approach,” Proc. WCM-Nanotech2006, vol. 3, pp.
792–795, Boston, MA, May 2006.
J. He, W. Bian, Y. Chen, B. Li, Y. D. Tao, and Y. Wei, "Carrier-based
compact modeling of charge and capacitance of long channel undoped symmetric
double-gate MOSFETs," Semicond. Sci. Technol., vol. 23, no. 4, 045003,
 G. J. Zhu, G. H. See, S. H. Lin, and X.
Zhou, "“Ground-Referenced” Model for Three-Terminal Symmetric Double-Gate
MOSFETs with Source/Drain Symmetry," IEEE Trans. Electron Devices, Vol.
55, No. 9, pp.
2526-2530, September 2008.
 H. Borli, S. Kolberg, and T. A. Fjeldly,
"Physics Based Current and Capacitance Model of Short-Channel Double Gate
and Gate-All-Around MOSFETs," 2008 IEEE-Nano, vols. 1-3, Shanghai, China,
Mar. 2008, pp. 493-498.
 H. Borli, S. Kolberg, T. A. Fjeldly, and B.
Iniguez, "Precise Modeling Framework for Short-Channel Double-Gate
and Gate-All-Around MOSFETs," IEEE Trans. Electron Devices, Vol. 55, No.
10, 2678-2686, Oct. 2008.