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[ Publications ] [ Book and Book Chapters | Int. Journals | Int. Conferences | Local Journals & Technical Reports | Local Conferences ] |
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Book and Book Chapters:BC3. C. H. Chang, M. Shibu and R. Xiao, "Self organizing feature map for color quantization on FPGA," in FPGA Implementations of Neural Networks, A. R. Omondi and J. C. Rajapakse, Ed., Chapter 8, pp. 225-245, Springer, The Netherlands, 2006. BC2. R. K. Satzoda and C. H. Chang, “VLSI performance evaluation of systolic and semisystolic finite field multipliers,” in Advances in Computer Systems Architecture, Lecture Notes in Computer Science LNCS 3740, T. Srikanthan, J. Xue and C. H. Chang, Ed., pp. 693-706, Springer-Verlag, Berlin, 2005. BC1. B. J. Falkowski and C. H. Chang, "Generation of fixed polarity Reed-Muller expansions from subset of Walsh spectral coefficients for completely specified Boolean functions," Invited Chapter, in "Advances in Spectral Techniques", C. Moraga, Ed., Special Issue of Book Series Berichte zur angewandten Informatik, (Reports on Applied Computer Science), pp. 21-26, University of Dortmund Publisher, Dortmund, Germany, 1998.
Papers
in Refereed International Journals:
J57. F. Li, A. Basu, C. H. Chang and A. H. Cohen, “Dynamical systems guided design and analysis of silicon oscillators for central pattern generators,” IEEE Transactions on Circuits and Systems–I: Regular Papers, 2012 (Accepted for publication).
J56. H. Qian, C. H. Chang and H. Yu, “An efficient channel clustering and flow rate allocation algorithm for non-uniform microfluidic cooling of 3D integrated circuits,” Special Issue on Thermal Modeling and Simulation, Thermal-Aware Design, and Thermal Management for 2D/3D ICs, Integration, The VLSI Journal, 2012 (Regular Paper, Accepted for Publication).
J55. R. Muralidharan and C. H. Chang, “Area-power efficient modulo 2n1 and modulo 2n+1multipliers for {2n1, 2n, 2n+1} based RNS,” IEEE Transactions on Circuits and Systems–I: Regular Papers, 2011 (Accepted for publication).
J54. R. Huang, C. H. Chang, M. Faust, N. Lotze and Y. Manoli,
“Sign-extension avoidance and word-length
opitmization by positive offset representation for FIR filter design,” IEEE
Transactions on Circuits and Systems–II:
Express Brief, vol. 58, no. 12, pp. 916-920, December
2012.
J53.
C. H. Chang and J.
Y. S. Low, “Simple, fast and exact RNS scaler for the
three-moduli set {2n-1, 2n,
2n+1},” IEEE
Transactions on Circuits and Systems–I: Regular Papers, vol.
58, no. 11, pp. 2686-2697, November 2011.
J52. M.
R. Meher, C. C. Jong, C. H. Chang,
“A high bit rate serial-serial multiplier with on-the-fly accumulation by
asynchronous counters,” IEEE
J51. R.
Muralidharan and C. H. Chang, “Radix-8
Booth encoded modulo 2n-1 multipliers with adaptive
delay for high dynamic range residue number system,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol.
58, no. 5, pp. 982-993, May 2011.
J50. A.
Cui, C. H. Chang, S. Tahar and A. A.
Hamid, “A robust FSM watermarking scheme for IP protection of sequential
circuit design,” I
J49. Y.
Shao and C. H. Chang, “Bayesian
separation with sparsity promotion in perceptual wavelet domain for speech
enhancement and hybrid speech recognition,” IEEE Transactions on Systems, Man and Cybernetics, Part A: Systems
and Human, vol. 41, no. 2, pp. 284-293, March 2011
(Regular paper).
J48. H. Qian, X. Huang, H. Yu and C. H. Chang,
“Cyber-physical Thermal Management of 3D Mult-core Cache Processor System
with Microfluidic Cooling,”ASP Journal
of Low Power Electronics, vol. 7, no. 1, pp. 110-121, February 2011 (Regular
paper).
J47. M.
Faust, O. Gustafsson and C. H. Chang,
“Fast and VLSI efficient binary-to-CSD encoder using bypass signal,” IET
Electronics Letters, vol. 47, no. 1, January 2011 (featured in
the in-brief section of the issue).
J46
C.
H. Chang and
R. K. Satzoda, “A low error and high performance multiplexer-based truncated
multiplier,” IEEE Transactions on Very Large
Scale Integration (VLSI) Systems, vol. 18, no.
12, pp. 1767-1771, December 2010.
J45.
C.
H. Chang and
A. Cui, “Synthesis-for-testability watermarking for field authentication of
VLSI intellectual property,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 57, no. 7, pp.
1618-1630, July 2010.
J44. C.
H. Chang and
M. Faust, “On ‘A new common subexpression elimination algorithm for realizing
low-complexity higher order digital filters’,” IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 5, pp. 844-848, May 2010.
J43. J.
Chen and C. H. Chang, “High-level synthesis algorithm for the design
of reconfigurable constant multiplier,” IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no.
12, pp. 1844-1856, December 2009 (Regular Paper).
J42. Y.
He and C. H. Chang, “A new redundant binary Booth encoding for fast 2n-bit
multiplier design,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 56, no. 6, pp.
1192-1201, June 2009. J41. A.
Cui, C. H. Chang and S. Tahar, “IP watermarking using incremental
technology mapping at logic synthesis level,” IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, vol. 27, no. 9, pp 1565-1570,
September 2008 (Regular paper).
J40. C.
H. Chang, J.
Chen and A. P. Vinod, “Information theoretic approach to complexity reduction
of FIR filter design,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 55, no. 8, pp.
2310-2321, September 2008.
J39. F.
Xu, C. H. Chang and C. C. Jong, “Contention resolution
– a new approach to versatile
subexpressions sharing in multiple constant multiplications,” IEEE Transactions
on Circuits and Systems–I:
Regular Papers,
vol. 55, no. 2, pp. 559 – 571, March 2008.
J38. Y.
He and C. H. Chang, “A power-delay efficient hybrid
carry-lookahead/carry-select based redundant binary to two's complement
converter,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 55, no. 1, pp. 336-346,
February 2008.
J37. F.
Xu, C. H. Chang and C. C. Jong, “Design of low-complexity FIR filters
based on signed-powers-of-two coefficients with reusable common
subexpressions,” IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, vol. 26, no. 10, pp. 1898-1907, October 2007.
J36. Y.
Shao and C. H. Chang, “A generalized time-frequency subtraction method
for robust speech enhancement based on Wavelet filter bank modeling of human
auditory system,” IEEE Transactions on Systems, Man and Cybernetics, Part
B: Cybernetics, vol. 37, no. 4, pp. 877- 889, August 2007 (Regular
paper).
J35. B.
Cao, C. H. Chang and T. Srikanthan, “A residue-to-binary converter for
a new 5-moduli set,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 54, no. 5, pp.
1041-1049, May 2007.
J34. F.
Xu, C. H. Chang and C. C. Jong, “Hamming weight pyramid
– a new insight into canonical
signed digit representation and its applications,” Journal of Computers
and Electrical Engineering, vol. 33, no. 3, pp. 195-207, May 2007
(Regular Paper).
J33. A.
P. Vinod, A. Singla and C. H. Chang, “Low power differential
coefficients-based FIR filters using hardware optimized multipliers,” IEE
Proceedings, Circuits, Devices and Systems, vol. 1, no. 1, pp.
13-22, February 2007
(Regular Paper).
J32. R.
K. Satzoda, C. H. Chang and C. C. Jong, “High throughput and low
complexity bit parallel and bit serial systolic architectures for Montgomery
modular multiplication,” WSEAS Transactions on Circuits and Systems,
vol. 5, no. 5, pp. 734-741, May 2006 (Invited Regular Paper).
J31.
Z.
H. Kong, K. S. Yeo and C. H. Chang, “An ultra low-power current-mode
sense amplifier for SRAM applications,” Journal of Circuits, Systems and
Computers, vol. 14, no. 5, pp. 939-951, October 2005
(Regular Paper).
J30. F.
Xu, C. H. Chang and C. C. Jong, “Contention resolution algorithms for
common subexpression elimination in digital filter design,” IEEE Transactions on Circuits and Systems-II Express
Brief, vol. 52, no. 10, pp. 695-700,
October 2005.
J29. B.
Cao, T. Srikanthan and C. H. Chang, “Efficient reverse
converters for the four-moduli sets
J28. C.
H. Chang, J.
Gu and M. Zhang, “A review of 0.18mm full adder
performances for tree structured arithmetic circuits,” IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, vol. 13, no. 6, pp. 686-695,
June 2005 (Regular Paper).
J27. P.
Xu, C. H. Chang and A. Paplinski, “Self-organizing topological tree
for online vector quantization and data clustering,” Special Issue on
Learning in Computer Vision and Pattern Recognition, IEEE Transactions on
Systems, Man and Cybernetics, Part B: Cybernetics, vol. 35, no. 3, pp.
515-526, June 2005 (Regular Paper). J26.
Z.
H. Kong, K. S. Yeo and C. H. Chang, “Design of an area-efficient CMOS
multiple-valued current comparator circuit,” IEE Proceedings, Circuits,
Devices and Systems, vol. 152, no. 2, pp. 151-158, April 2005
(Regular Paper).
J25. F.
Xu, C. H. Chang and C. C. Jong, “Modified reduced adder graph
algorithm for multiplierless FIR filters,” IEE Electronics Letters,
vol. 41, no. 6, pp. 302-303, March 2005.
J24.
C.
H. Chang, P.
Xu, R. Xiao and T. Srikanthan, “New adaptive color quantization method based
on self-organizing maps,” IEEE Transactions on Neural Networks, vol.
16, no. 1, pp. 237-249, January 2005 (Regular Paper).
J23. C.
H. Chang, Z.
Ye and M. Zhang, “Fuzzy-ART based adaptive digital watermarking scheme,” IEEE Transactions on Circuits and Systems for Video
Technology, vol. 15, no. 1, pp. 65-81,
January 2005 (Regular Paper).
J22.
C.
H. Chang, J.
Gu and M. Zhang, “Ultra low voltage, low power CMOS 4-2 and 5-2 compressors
for fast arithmetic circuits,” IEEE Transactions
on Circuits and Systems-I: Regular Papers,
vol. 51, no. 10, pp. 1985-1997, October 2004.
J21. J.
Gu, C. H. Chang and K. S. Yeo, “Algorithm and architecture of a high
density, low power scalar product macrocell,” IEE Proceedings, Computers
and Digital Techniques, vol. 151, no. 2, pp. 161-172, March 2004
(Regular Paper).
J20. B.
Cao, C. H. Chang and T. Srikanthan, “An efficient reverse converter
for the 4-moduli set {2n-1, 2n, 2n+1, 22n+1}
based on the New Chinese Remainder Theorem,” IEEE Transactions on Circuits
and Systems–I: Fundamental Theory and
Applications,
vol. 50, no. 10, pp. 1296-1303, October 2003 (Regular paper)
J19. C.
H. Chang, H.
Tian, T. Srikanthan and C. S. Lim, “A FPGA based architecture for real time
image segmentation by region growing algorithm,” Journal of Electronic
Imaging, vol. 11, no. 4, pp. 469-478, October 2002
(Regular Paper).
J18. C.
H. Chang and
B. J. Falkowski, “Boolean matching filters based on row and column weights of
Reed-Muller polarity coefficient matrix,” VLSI Design, An
International Journal of Custom-Chip Design, Simulation and Testing, vol.
14, no. 3, pp. 259-271, May 2002
(Regular Paper).
J17. B.
J. Falkowski and C. H. Chang, “Minimization of k-variable
mixed-polarity Reed-Muller expansions,” VLSI Design, An
International Journal of Custom-Chip Design, Simulation and Testing, vol.
11, no. 4, pp. 311-320, October 2000
(Regular Paper).
J16. B.
J. Falkowski and C. H. Chang, “Generalized k-variable-mixed-polarity
Reed-Muller expansions for systems of Boolean functions and their
minimization,” IEE Proceedings, Circuits, Devices and Systems, vol.
147, no. 4, pp. 201-210, August 2000
(Regular Paper).
J15. B.
J. Falkowski and C. H. Chang, “Paired Haar spectra computation through
operations on disjoint cubes,” IEE Proceedings, Circuits, Devices and
Systems, vol. 146, no. 3, pp. 117-123, June 1999
(Regular Paper). J14. C.
H. Chang and
B. J. Falkowski, “NPN Classification using weight and literal vectors of
Reed-Muller expansion,” IEE Electronics Letters, vol 35, no. 10, pp.
798-799, May 1999.
J13. B.
J. Falkowski and C. H. Chang, “Efficient algorithm for the calculation
of generalized Adding and Arithmetic transforms from disjoint cubes of
Boolean functions,” VLSI Design, An International Journal of
Custom-Chip Design, Simulation and Testing, vol. 9, no. 2, pp. 135-146,
April 1999 (Regular
Paper).
J12. B.
J. Falkowski and C. H. Chang, “Hadamard-Walsh spectral
characterization of Reed-Muller expansions,” Computers and Electrical
Engineering, An International Journal, vol. 25, no. 2, pp. 111-134, March
1999 (Regular
Paper).
J11. B.
J. Falkowski and C. H. Chang, “Properties and calculation of Paired
Haar transform,” Journal of Approximation Theory and Its Applications,
vol. 15, no. 2, pp. 1-14, February 1999
(Regular Paper).
J10. C.
H. Chang and
B. J. Falkowski, “Haar spectra based entropy approach to quasi-minimisation
of FBDDs,” IEE Proceedings, Computers and Digital Techniques, United
Kingdom, vol. 146, no. 1, pp. 41-49, January 1999
(Regular Paper). J9. C.
H. Chang and
B. J. Falkowski, “Adaptive exact optimization of Reed-Muller expansions for
system of functions,” IEE Proceedings, Computers and Digital Techniques,
vol. 145, no. 6, pp. 385-394, November 1998
(Regular Paper). J8. C.
H. Chang and
B. J. Falkowski, “Logical manipulations and design of tributary network in
Arithmetic spectral domain,” IEE Proceedings, Computers and Digital
Techniques, vol. 145, no. 5, pp. 347-356, September 1998
(Regular Paper). J7.
B.
J. Falkowski and C. H. Chang, “Mutual conversions between generalized
Arithmetic expansions and free binary decision diagrams,” IEE Proceedings,
Circuits, Devices and Systems, vol. 145, no. 4, pp. 219-228, August 1998
(Regular Paper). J6.
B.
J. Falkowski and C. H. Chang, “Efficient calculation of Gray code
ordered Walsh spectra through Algebraic Decision Diagram,” IEE Electronics
Letters, vol. 34, no. 9, pp. 848-850, April 1998. J5.
B.
J. Falkowski and C. H. Chang, “Forward and inverse transformations
between Haar spectra and ordered binary decision diagrams of Boolean
functions,” IEEE Transactions on Computers, vol. 46, no. 11, pp.
1272-1279, November 1997. J4.
C.
H. Chang and B.
J. Falkowski, “Efficient symbolic computation of generalized spectra,” IEE
Electronics Letters, vol. 33, no. 22, pp. 1837-1838, October 1997. J3.
B.
J. Falkowski and C. H. Chang, “Properties and methods of calculating
generalized arithmetic and adding transforms,” IEE Proceedings, Circuits,
Devices and Systems, vol. 144, no. 5, pp. 249-258, October 1997
(Regular Paper). J2.
B.
J. Falkowski and C. H. Chang, “Exact minimizer of fixed polarity
Reed-Muller expansions,” International Journal of Electronics, vol.
79, no. 4, pp. 389-409, October 1995 (Regular Paper). J1. M. A. Do and C. H. Chang, “Design and performance of a new multi-lane AVI system,” Intelligent Vehicle Highway System (IVHS) Journal, vol 1, no. 2, pp. 151-166, 1993 (Regular Paper).
Papers in Refereed International Conferences:
C115. L. Zhang and C. H. Chang, “State encoding watermarking for field authentication of sequential circuit intellectual property,” in Proc. 2012 IEEE Int. Symp. on Circuits and Systems (ISCAS-2012), Seoul, Korea, 20-23 May 2011 (Accepted).
C114. M. Kumm, P. Zipf, M. Faust and C. H. Chang, “Pipelined adder graph optimization for high speed multiple constant multiplication,” in Proc. 2012 IEEE Int. Symp. on Circuits and Systems (ISCAS-2012), Seoul, Korea, 20-23 May 2011 (Accepted).
C113.
J. Y. L. Low, C. C. Jong, J. Y. S. Low, T. F. Tay and C. H. Chang, “A
fast and compact circuit for integer square root computation based on
Mitchell logarithmic method,” in Proc. 2012 IEEE Int. Symp. on Circuits
and Systems (ISCAS-2012), Seoul, Korea, 20-23 May 2011 (Accepted).
C112. F. Li, A. Basu, C. H. Chang and A. H. Cohen, “Dynamical systems: a tool for
analysis and design of silicon half center oscillators,” in Proc. 2011 IEEE Biomedical Circuits &
Systems Conference (BioCAS 2011), Diego, California, pp. 249-252, 10-12
November, 2011. C111. M. Faust and C. H. Chang, “Low error bit width reduction for structural adders of FIR filters,” in Proc. 20th European Conference on Circuit Theory and Design (ECCTD 2011), Linköping, Sweden, pp. 713-716, 29-31 August 2011.
C110.
J. Y. S. Low and C. H. Chang, “A new RNS scaler for {2n–1, 2n, 2n+1},”
in Proc. 2011 IEEE Int. Symp. on Circuits and Systems (ISCAS-2011), Rio de
Janeiro, Brazil, pp. 1431-1434, 15-18 May 2011.
C109. R. Muralidharan and C. H. Chang, “A simple radix-4 Booth
encoded modulo 2n+1 multiplier,”
in Proc. 2011 IEEE Int. Symp. on Circuits and Systems (ISCAS-2011), Rio de
Janeiro, Brazil, pp. 1163-1166, 15-18 May 2011.
C108. M. Faust and C. H. Chang, “Bit-parallel multiple constant multiplication using
Look-Up tables on FPGA,” in Proc. 2011 IEEE Int. Symp. on Circuits and
Systems (ISCAS-2011), Rio de Janeiro, Brazil, pp. 657-660, 15-18 May
2011.
C107. A. Cui, C. H. Chang and L. Zhang, “A hybrid watermarking scheme for
sequential functions,” in Proc. 2011 IEEE Int. Symp. on Circuits and
Systems (ISCAS-2011), Rio de Janeiro, Brazil, pp. 2333-2336, 15-18 May
2011.
C106.
H.
Qian, X. Huang, H. Yu and C. H. Chang,
“Real-time thermal management of 3D multi-core system with fine-grained
cooling control,” in Proc. 2010 IEEE International
3D System Integration Conference, Munich, Germany, pp. 1-6,
16-18 November 2010.
C105.
M.
Faust, O. Gustafsson and C. H. Chang,
“Reconfigurable multiple constant multiplication using minimum adder depth,”
in Proc. 44th Asilomar Conference on
Signals, Systems and Computers, Pacific Grove, California, USA, 7-10
November 2010.
C104. F.
Li, C. H. Chang and S. Liter, “A
very low power 0.7 V subthreshold fully programmable Gaussian function
generator” in Proc. 2nd IEEE Asia Pacific Conference on
Postgraduate Research in Microelectronics & Electronics (PrimeAsia
2010), Shanghai, China, pp. 198-201, 22-24 September 2010 (Gold Leaf
Certificate Award – top 10%).
C103. M.
Faust and C. H. Chang, “Reduction
of partial product matrix for high-speed single or multiple constant
multiplication” in Proc. 2nd IEEE Asia Pacific Conference on
Postgraduate Research in Microelectronics & Electronics (PrimeAsia
2010), Shanghai, China, pp. 416-420,
22-24 September 2010 (Silver Leaf Certificate Award – top 10-20%).
C102. B. Cao, Y. S. Low, C. H. Chang and T. Srikanthan,
“Performance
analysis of different special moduli sets for RNS-based inner product step
processor,” in Proc.
2010 International Conference on Green Circuits and Systems (ICGCS-2010),
Shanghai, China, pp. 236-241, 21-23 June, 2010
C101. M.
R. Meher, C. C. Jong, C. H. Chang and J. Y. S. Low,
“A novel counter-based low
complexity inner-product architecture for high speed inputs,” in Proc. 2010 IEEE
Int. Symp. on Circuits and Systems (ISCAS-2010), Paris, France, pp.
705-708,
30 May-2 June 2010
C100. M.
Faust and C. H. Chang, “Minimal
logic depth adder tree optimization for multiple constant multiplication,” in Proc. 2010 IEEE
Int. Symp. on Circuits and Systems (ISCAS-2010), Paris, France, pp.
457-460, 30 May-2
June 2010.
C99.
R.
Muralidharan and C. H. Chang,
“Fast hard multiple generators for radix-8 Booth
encoded modulo 2n-1 and modulo 2n+1 multipliers,” in Proc. 2010 IEEE
Int. Symp. on Circuits and Systems (ISCAS-2010), Paris, France, pp.
717-720, 30 May-2 June 2010.
C98.
R.
Muralidharan and C. H. Chang,
“Hard multiple generator for higher radix modulo 2n-1
multiplication,” in Proc. 2009 Int. Symp. on
Integrated Circuits (ISIC 2009), Singapore, pp. 546-549, 14-16, Dec.
2009.
C97.
T.
B. Juang, C. H. Chang and C. C. Wei,
“Area-saving technique for low-error redundant
binary fixed-width multiplier implementation,” in Proc. 2009 Int. Symp. on Integrated
Circuits (ISIC 2009), pp. 550-553, Singapore,
14-16, Dec. 2009.
C96.
J.
Chen, C. H. Chang and C. C. Jong, “Time-multiplexed data flow graph
for the design of configurable multiplier block,” in Proc. Int. Symp. on
Circuits and Systems (ISCAS-2009), Taipei, Taiwan, pp, 1145-1148, 24-27
May 2009.
C95.
M.
Faust and C. H. Chang, “Optimization
of structural adders in fixed coefficient transposed direct form FIR filters,” in Proc. Int. Symp. on
Circuits and Systems (ISCAS-2009), Taipei, Taiwan, pp. 2185-2188, 24-27
May 2009.
C94.
F.
Li, C. H. Chang and S. Liter,
“A compact current mode neuron circuit with
Gaussian taper learning capability,”
in Proc. Int. Symp. on Circuits and Systems (ISCAS-2009), Taipei,
Taiwan, pp. 2129-2132, 24-27 May 2009.
C93.
J.
Chen, C. H. Chang and H. Qian,
“New power index model for switching power analysis
from adder graph of FIR filter,”
in Proc. Int. Symp. on Circuits and Systems (ISCAS-2009), Taipei,
Taiwan, pp. 2197-2200, 24-27 May 2009.
C92.
A.
Cui and C. H. Chang, “An
improved publicly detectable watermarking scheme based on scan chain
ordering,” in Proc. Int. Symp. on
Circuits and Systems (ISCAS-2009), Taipei, Taiwan, pp. 29-32, 24-27 May
2009.
C91.
R.
Muralidharan and C. H. Chang,
“Fixed and variable multi-modulus squarer
architectures for triple moduli base of RNS,” in Proc. Int. Symp. on Circuits and Systems
(ISCAS-2009), Taipei, Taiwan, pp. 441-444, 24-27 May 2009.
C90.
R.
Muralidharan, C. H. Chang and C. C. Jong,
“A low complexity modulo 2n+1 squarer
design,” in Proc. 2008 IEEE Asia
Pacific Conference on Circuits and Systems (APCCAS-2008), Macao, China,
pp. 1296-1299, 30 Nov.-3 Dec. 2008.
C89.
M.
R. Meher, C. C. Jong and C. H. Chang,
“High-speed and low-power serial accumulator for
serial-parallel multiplier,”
in Proc. 2008 IEEE Asia Pacific Conference on Circuits and Systems
(APCCAS-2008), Macao, China, pp. 176-179, 30 Nov.-3 Dec. 2008.
C88.
A.
Cui and C. H. Chang, “Intellectual property authentical by
watermarking scan chain in design-for-testability flow,” in Proc. IEEE
Int. Symp. on Circuits and Systems (ISCAS-2008), Seattle, USA, pp.
2645-2648,18-21 May 2008.
C87.
R.
K. Satzoda, R. Muralidharan and C. H. Chang, “Programmable LSB-first
and MSB-first modular multiplier for ECC in GF(2m),” in Proc. IEEE
Int. Symp. on Circuits and Systems (ISCAS-2008), Seattle, USA, pp.
808-811, 18-21 May 2008.
C86.
R.
K. Satzoda, H. N. Quang and C. H. Chang,
“Programmable Montgomery modular multiplier for
trinomonial reduction polynomials in GF(2m),” in Proc. 2007 Int. Conf. on
Integrated Circuits (ISIC-2007), Singapore, 26-29 Sept. 2007.
C85.
A.
Cui and C. H. Chang, “Watermarking
for IP protection through template substitution at logic synthesis level”, in Proc. IEEE Int.
Symp. on Circuits and Systems (ISCAS-2007), New Orleans, USA, pp.
3687-3690,
27-30 May 2007.
C84.
S.
Menon and C. H. Chang, “A
reconfigurable multi-modulus modulo multiplier,” in Proc. 2006 IEEE Asia-Pacific Conf. on
Circuits and Systems (APCCAS-2006), Singapore, pp. 1170-1173, December
4-7, 2006.
C83.
A.
Cui and C. H. Chang, “Kernel
extraction for watermarking combinational logic networks,” in Proc. 2006 IEEE
Asia-Pacific Conf. on Circuits and Systems (APCCAS-2006), Singapore, pp.
1025-1028, December 4-7, 2006.
C82.
U.
Meyer-Baese, J. Chen, C. H. Chang and A. G. Dempster,
“A comparison of pipelined RAG-n
and DA FPGA-based multiplierless filters,” in Proc. 2006 IEEE Asia-Pacific Conf. on
Circuits and Systems (APCCAS-2006), Singapore, pp. 1557-1560, December
4-7, 2006.
C81.
J.
Chen, C. H. Chang and A. P. Vinod,
“Design of high-speed, low-power FIR filters with
fine-grained cost metrics,”
in Proc. 2006 IEEE Asia-Pacific Conf. on Circuits and Systems
(APCCAS-2006), Singapore, pp. 757-760, December 4-7, 2006.
C80.
A.
P. Vinod, C. H. Chang, P. K. Meher and A. Singla,
“Low power FIR filter
realization using minimal difference coefficients: Part I-Complexity
Analysis,” in Proc. 2006 IEEE
Asia-Pacific Conf. on Circuits and Systems (APCCAS-2006), Singapore, pp.
1549-1552, December 4-7, 2006.
C79. A.
P. Vinod, C. H. Chang, P. K. Meher and A. Singla,“Low power FIR filter realization
using minimal difference coefficients: Part II-Algorithm,” in Proc. 2006 IEEE
Asia-Pacific Conf. on Circuits and Systems (APCCAS-2006), Singapore, pp.
1553-1556, December 4-7, 2006.
C78.
R.
K. Satzoda, C. H. Chang and C. C. Jong,
“High Speed Systolic Montgomery Modular Multipliers
for RSA Cryptosystems,”
in Proc. 5th WSEAS Int. Conf. on Instrumentation, Measurement, Circuits
and Systems, (IMCAS '06), Hangzhou, China, pp. 240-245, April 16-18,
2006 (Invited paper).
C77.
Y.
Shao and C. H. Chang, “A
novel hybrid neuro-wavelet system for robust speech recognition,” in Proc. IEEE Int. Symp. on
Circuits and Systems (ISCAS-2006), Kos, Greece, pp. 1852-1855, May 21-24,
2006. C76.
Y.
Shao and C. H. Chang, “A
Kalman filter based on wavelet filter-bank and psychoacoustic modeling for
speech enhancement,” in Proc. IEEE Int. Symp. on
Circuits and Systems (ISCAS-2006), Kos, Greece, pp. 121-124, May 21-24,
2006.
C75.
Y.
Shao and C. H. Chang, “A
generalized perceptual time-frequency subtraction method for speech
enhancement,” in Proc. IEEE Int. Symp. on
Circuits and Systems (ISCAS-2006), Kos, Greece, pp. 2537-2540, May 21-24,
2006.
C74.
F.
Xu, C. H. Chang and C. C. Jong,
“A new integrated approach to the design of
low-complexity FIR filters,”
in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS-2006), Kos,
Greece, pp. 601-604, May 21-24, 2006.
C73. Y.
He and C. H. Chang, “A
low-power, high-speed RB-to-NB converter for fast redundant binary
multiplier,” in Proc. IEEE Int. Symp. on
Circuits and Systems (ISCAS-2006), Kos, Greece, pp. 2405-2408, May 21-24,
2006.
C72. C.
H. Chang, J.
Chen and A. P. Vinod, “Maximum
likelihood disjunctive decomposition to reduced multirooted DAG for FIR
filter design,” in Proc. IEEE Int. Symp. on
Circuits and Systems (ISCAS-2006), Kos, Greece, pp. 613-616, May 21-24,
2006.
C71.
R.
K. Satzoda and C. H. Chang, “A
fast kernel for unifying GF(p) and GF(2m) montgomery
multiplications in a scalable pipelined architecture,” in Proc. IEEE Int. Symp. on Circuits and
Systems (ISCAS-2006), Kos, Greece, pp. 3378-3381, May 21-24, 2006.
C70.
A.
Cui and C. H. Chang, “Stego-signature
at logic synthesis level for digital design IP protection,” in Proc. IEEE Int. Symp. on
Circuits and Systems (ISCAS-2006), Kos, Greece, pp. 4611-4614, May 21-24,
2006.
C69.
A.
P. Vinod, C. H. Chang and A. Singla,
“Improved differential coefficients-based low power
FIR filters: Part I –
Fundamentals,” in Proc. IEEE Int. Symp. on
Circuits and Systems (ISCAS-2006), Kos, Greece, pp. 617-620, May 21-24,
2006.
C68.
Y.
He, C. H. Chang, J. Gu and H. A. H. Fahmy,
“A novel covalent redundant binary Booth encoder,” in Proc. IEEE Int. Symp. on
Circuits and Systems (ISCAS-2005), Kobe, Japan, pp. 69-72, May 23-26,
2005. C67.
Y.
He, C. H. Chang and J. Gu, “An
area efficient 64-bit square root carry-select adder for low power
applications,” in Proc. IEEE Int. Symp. on
Circuits and Systems (ISCAS-2005), Kobe, Japan, pp. 4082-4085, May
23-26, 2005.
C66. B.
Cao, T. Srikanthan and C. H. Chang,
“A new design method to modulo 2n-1
squaring,” in Proc. IEEE Int. Symp. on
Circuits and Systems (ISCAS-2005), Kobe, Japan, pp. 664-667, May 23-26,
2005.
C65.
B.
Cao, C. H. Chang and T. Srikanthan,
“A new formulation of fast diminished-one
multioperand modulo 2n+1 adder,” in Proc. IEEE Int. Symp. on Circuits and
Systems (ISCAS-2005), Kobe, Japan, pp. 656- 659, May 23-26, 2005.
C64.
C.
H. Chang, R.
K. Satzoda and S. Sekar, “A
novel multiplexer based truncated array multiplier,” in Proc. IEEE Int. Symp. on Circuits and
Systems (ISCAS-2005), Kobe, Japan, pp. 85-88, May 23-26, 2005.
C63.
Y.
Shao and C. H. Chang, “Wavelet
transform to hybrid support vector machine and hidden Markov model for speech
recognition,” in Proc. IEEE Int. Symp. on
Circuits and Systems (ISCAS-2005), Kobe, Japan, pp. 3833-3836, May 23-26,
2005.
C62.
Y.
Shao and C. H. Chang, “A
versatile speech enhancement system based on perceptual wavelet denoising,” in Proc. IEEE Int. Symp. on
Circuits and Systems (ISCAS-2005), Kobe, Japan, pp. 864-867, May 23-26,
2005.
C61.
C.
H. Chang, S.
Menon, B. Cao and T. Srikanthan, “A
configurable dual moduli multi-operand modulo adder,” in Proc. IEEE Int. Symp. on Circuits and
Systems (ISCAS-2005), Kobe, Japan, pp. 1630-1633, May 23-26, 2005.
C60. F.
Xu, C. H. Chang and C. C. Jong,
“I2CRA: Contention resolution algorithm
for intra- and inter-coefficient common subexpression elimination,” Special Session on Low
Complexity Digital Filter Design Techniques and Their Applications, in Proc.
IEEE Int. Symp. on Circuits and Systems (ISCAS-2005), Kobe, Japan, pp.
1823-1826, May 23-26, pp. 2005.
C59. S.
Udit, F. Xu, C. H. Chang, C. C. Jong and K. S. Yeo,
“sys-fir: A compiler for evaluating VLSI performance metrics of
reduced adder cost FIR filters,”
in Proc. IEEE Int. Symp. on Low-power and High-speed Chips
(Cool Chips VIII), Yokohama Joho Bunka Centre, Yokohama, Japan, pp.339-346,
April 20-22, 2005.
C58.
X.
Deng, P. Xu, and C. H. Chang,
“Self organizing topological tree for skin color
detection,” in Proc. IEEE Asia-Pacific
Conf. on Circuits and Systems (APCCAS-2004), Tainan, Taiwan, pp.
1097-1100, December 6-9, 2004.
C57.
F.
Xu, J. Chen, C. H. Chang and C. C. Jong,
“A modified reduced adder graph algorithm for
multiplier block minimization in digital filters,” in Proc. IEEE Asia-Pacific Conf. on Circuits
and Systems (APCCAS-2004), Tainan, Taiwan, pp. 705-708, December 6-9,
2004.
C56. C.
H. Chang, Y.
He and J. Gu, “An alternative scheme for
redundant binary multiplier,”
in Proc. IEEE Asia-Pacific Conf. on Circuits and Systems
(APCCAS-2004), Tainan, Taiwan, pp. 33-36, December 6-9, 2004.
C55.
B.
Cao, T. Srikanthan and C. H. Chang,
“Design of residue-to-binary converter for a new
5-moduli superset residue number system,” in Proc. 37th IEEE Int. Symp. on Circuits and
Systems (ISCAS-2004), Vancouver, Canada, Vol. II, pp. 841-844, May 23-26,
2004.
C54.
F.
Xu, C. H. Chang and C. C. Jong,
“A new contention resolution algorithm for the
design of minimal logic depth multiplierless filters,” in Proc. 37th IEEE Int. Symp. on Circuits and
Systems (ISCAS-2004), Vancouver, Canada, Vol III, pp.481-484, May 23-26,
2004.
C53.
F.
Xu, C. H. Chang and C. C. Jong,
“HWP: a new insight into canonical signed digit,” in Proc. 37th IEEE Int.
Symp. on Circuits and Systems (ISCAS-2004), Vancouver, Canada, Vol. V,
pp. 201-204, May 23-26, 2004.
C52. C.
H. Chang and
P. Xu, “Frequency
sensitive self-organzing maps
and its application in color quantization,” in Proc. 37th IEEE Int. Symp. on Circuits and
Systems (ISCAS-2004), Vancouver, Canada, Vol. V, pp804-807, May 23-26,
2004.
C51.
P.
Xu and C. H. Chang, “Self-organizing
topological tree,” in Proc. 37th IEEE Int.
Symp. on Circuits and Systems (ISCAS-2004), Vancouver, Canada, Vol. V,
pp. 732-735, May 23-26, 2004.
C50.
F.
Xu, C. H. Chang and C. C. Jong,
“Efficient algorithm for common subexpression
elimination in digital filter design,” in Proc. IEEE Int. Conf. on Acoustics, Speech
and Signal Processing (ICASSP-2004), Montreal, Canada, Vol. V, pp.
137-140, May 17-21, 2004.
C49.
J.
Gu, C. H. Chang and K. S. Yeo,
“An area and energy efficient IP core for scalar
product computation,”
in Proc. IEEE Int. Symp. on Low-power and High-speed Chips, Cool Chips VII,
Yokohama, Japan, Vol. 1, pp.219-226, April 14-16, 2004.
C48. X.
Deng, C. H. Chang and E. Brandle,
“A new method for eye extraction from facial image,” in Proc. 2nd
IEEE Int. Workshop on Electronic Design, Test and Applications
(DELTA-2004), Perth, Australia, pp. 29-34, January 2004.
C47. Z.
Ye and C. H. Chang, “Local
search method for FIR filter coefficients synthesis,” in Proc. 2nd IEEE Int.
Workshop on Electronic Design, Test and Applications (DELTA-2004), Perth,
Australia, pp. 255-260, January 2004.
C46.
Z.
Ye, R. K. Satzoda, U. Sharma, N. Nazimudeen and C. H. Chang,
“Performance evaluation of
direct form FIR filter with merged arithmetic architecture,” in Proc. 2nd
IEEE Int. Workshop on Electronic Design, Test and Applications
(DELTA-2004), Perth, Australia, pp. 407-409, January 2004.
C45. C.
H. Chang, M.
Zhang and J. Gu, “A novel low power low voltage
full adder cell,” in Proc. 3rd IEEE/EURASIP
Int. Symp. on Image and Signal Processing and Analysis (ISPA-2003), Rome,
Italy, pp. 454-458, September 2003.
C44.
B.
Cao, C. H. Chang and T. Srikanthan,
“Adder based residue to binary converters for a new
balanced 4-moduli set,”
in Proc. 3rd IEEE/EURASIP Int. Symp. on Image and Signal Processing and
Analysis (ISPA-2003), Rome, Italy, pp. 820-825, September 2003.
C43. Z.
Ye and C. H. Chang, “A
hybrid CSA tree for merged arithmetic architecture of FIR filter,” in Proc. 3rd IEEE/EURASIP
Int. Symp. on Image and Signal Processing and Analysis (ISPA-2003), Rome,
Italy, pp. 449-453, September 2003.
C42.
B.
Cao, T. Srikanthan and C. H. Chang,
“Design of a high speed reverse converter for a new
4-moduli set residue number system,”
in Proc. 36th IEEE Int. Symp. on Circuits and Systems (ISCAS-2003),
Bangkok, Thailand, Vol. IV, pp. 520-523, May 2003.
C41.
B.
Cao, C. H. Chang and T. Srikanthan,
“New efficient residue-to-binary converters for
4-moduli set {2n-1, 2n, 2n+1, 2n+1-1},” in Proc. 36th
IEEE Int. Symp. on Circuits and Systems (ISCAS-2003), Bangkok, Thailand,
Vol. IV, pp. 536-539, May 2003.
C40. M.
Zhang, J. Gu and C. H. Chang,
“A novel hybrid pass logic with static CMOS output
drive full-adder cell,”
in Proc. 36th IEEE Int. Symp. on Circuits and Systems (ISCAS-2003),
Bangkok, Thailand, Vol. V, pp. 317-320, May 2003.
C39.
J.
Gu and C. H. Chang, “Ultra
low voltage, low power 4-2 compressor for high speed multiplications,” in Proc. 36th
IEEE Int. Symp. on Circuits and Systems (ISCAS-2003), Bangkok, Thailand,
Vol. V, pp. 321-324, May 2003.
C38. M.
Shibu, C. H. Chang and R. Xiao,
“FPGA implementation of a frequency adaptive
learning SOFM for digital color still imaging,” in Proc. 36th IEEE Int. Symp. on
Circuits and Systems (ISCAS-2003), Bangkok, Thailand, Vol. II, pp.
452-455, May 2003.
C37.
C.
H. Chang, R.
Xiao and T. Srikanthan, “An
adaptive initialization technique for color quantization by self organizing
feature map,” in Proc. IEEE Int. Conf. on
Acoustics, Speech and Signal Processing (ICASSP-2003), Hong Kong, Vol
III, pp. 477-480, April 2003.
C36.
J.
Gu and C. H. Chang, “Low
voltage, low power (5:2) compressor cell for fast arithmetic circuits,” in Proc. IEEE Int. Conf. on
Acoustics, Speech and Signal Processing (ICASSP-2003), Hong Kong, Vol.
II, pp. 661-664, April 2003.
C35. X.
Yang and C. H. Chang, “A
feasibility study of embedded Linux for the software defined radio,” in Proc. 2003 IEEE Sarnoff
Symposium on Advances in Wired and Wireless Communications, New Jersey,
USA, pp. 131-134, March 2003.
C34. X.
Yang and C. H. Chang, “A
practical approach for automatic recognition and identification of digital
modulations,” in Proc. 2003 IEEE Sarnoff
Symposium on Advances in Wired and Wireless Communications, New Jersey,
USA, pp. 135-138, March 2003.
C33. C.
H. Chang, R.
Xiao and T. Srikanthan, “A
MSB-biased self-organizing feature map for still color image compression,” in Proc. IEEE Asia Pacific
Conf. on Circuits and Systems (APCCAS-2002), Bali, Indonesia, Vol. 2, pp.
85-88, October 2002.
C32. C.
H. Chang, Z.
Ye and M. Zhang, “Fuzzy-ART based digital
watermarking scheme,”
in Proc. IEEE Asia Pacific Conf. on Circuits and Systems (APCCAS-2002),
vol. 1, pp. 423-426, Bali, Indonesia, October 2002.
C31. H.
Tian, S. K. Lam, T. Srikanthan and C. H. Chang,
“An efficient architecture for
adaptive progressive thresholding,”
in Proc. IEEE Asia Pacific Conf. on Circuits and Systems (APCCAS-2002),
Bali, Indonesia, Vol. 1, pp. 513-516, October 2002. C30. A.
Ehrensperger, C. H. Chang, J. G. Ma, F. Schnyder and C. Haller,
“Fixed-point DSP implementation of mixed demodulator for digital FM radio
receiver,” in Proc. IEEE Int. Symp. on Consumer Electronics (ISCE'02),
Erfurt, Germany, pp. IF77-82, September 2002.
C29. X.
Yang and C. H. Chang, “Bluetooth enabled embedded Linux,” in Proc.
9th Int. Linux Systems Technology Conf. (Linux-Kongress 2002),
Cologne, Germany, pp. 14-29, September 2002.
C28. C.
H. Chang, M.
Zhang and Z. Ye, “A content-dependent robust and
fragile watermarking scheme,”
in Proc. 2nd IASTED Int. Conf. on Visualization, Imaging and
Image Processing (VIIP-2002), Malaga, Spain, pp. 201-206, September 2002.
C27. R.
Xiao, C. H. Chang and T. Srikanthan,
“A new localized learning scheme for
self-organizing feature maps,”
in Proc. 2nd IASTED Int. Conf. on Visualization, Imaging and
Image Processing (VIIP-2002), Malaga, Spain, pp. 261-264, September 2002.
C26. J.
Gu, C. H. Chang and K. S. Yeo,
“An interconnect optimized floorplanning of a
scalar product macrocell,”
in Proc. 35th IEEE Int. Symp. on Circuits and Systems (ISCAS'02), Scottsdale,
Arizona, USA., Vol. I, pp. 465-468, May 2002.
C25. R.
Xiao, C. H. Chang and T. Srikanthan,
“On the initialization and training methods for
Kohonen self-organizing feature maps in color image quantization,” in Proc. 1st
Int. Workshop on Electronic Design, Test and Applications (DELTA-2002),
Christchurch, New Zealand, pp. 321-325, January 2002.
C24. C.
H. Chang and
B. J. Falkowksi, “Graph based analysis and
computation of Reed-Muller weight vectors,” in Proc. 9th Int. Symp. on
Integrated Circuits, Devices and Systems (ISIC-2001), Singapore, pp.
484-487, September 2001.
C23. D.
J. Ho, C. H. Chang, H. Z. Peh and R. Meyyappan,
“Architecture of a hardware
module for GSM vocoder,”
in Proc. 9th Int. Symp. on Integrated Circuits, Devices and
Systems (ISIC-2001), Singapore, pp. 362- 365, September 2001.
C22.
C.
H. Chang and
B. J. Falkowksi, “Reed-Muller transform based Boolean matching filters,” in Proc.
15th European Conference on Circuit Theory and Design (ECCTD’01), Espoo, Finland, pp.
285-288, August 2001.
C21. C.
H. Chang and
B. J. Falkowski, "Reed-Muller weight and literal vectors for NPN
classification," in Proc. 32nd IEEE Int. Symp. on Circuits and
Systems (ISCAS'99), Orlando, Florida, USA, Vol. I, pp. 379-382, Jul 1999.
C20.
B.
J. Falkowski and C. H. Chang, "Optimization of partially-mixed
polarity Reed-Muller expansions," in Proc. 32nd IEEE Int. Symp. on
Circuits and Systems (ISCAS'99), Orlando, Florida, USA, Vol I, pp.
383-386, Jul 1999.
C19. C.
H. Chang and
B. J. Falkowski, "Generation of quasi-optimal FBDDs through paired Haar
spectra," in Proc. 31st IEEE Int. Symp. on Circuits and Systems
(ISCAS'98), Monterey, California, USA,Vol. VI, pp. 167-170, June 1998.
C18. B.
J. Falkowski and C. H. Chang, "Calculation of paired Haar spectra
for systems of incompletely specified Boolean functions," in Proc.
31st IEEE Int. Symp. on Circuits and Systems (ISCAS'98), Monterey,
California, USA, Vol. VI, pp. 171-174, June 1998.
C17.
C.
H. Chang and
B. J. Falkowski, "In-place transformation of generalized and complex
spectra through algebraic decision diagrams," in Proc. 1st IEEE Int.
Conf. on Information, Communications and Signal Processing (ISICS'97),
Singapore, Vol. 1, pp. 256-260, September 1997.
C16. B.
J. Falkowski and C. H. Chang, "Properties and applications of
paired Haar transform," in Proc. 1st Int. Conf. on Information,
Communications and Signal Processing (ISICS'97), Singapore, Vol. 1, pp.
48-51, September 1997.
C15.
C. H. Chang and B. J. Falkowski, "Boolean matching for
generic FPGAs," in Proc. 30th IEEE Int. Symp. on Circuits and Systems
(ISCAS'97), Hong Kong, Vol.3, pp. 1700-1703, June 1997.
C14. B. J. Falkowski
and C. H. Chang, "Calculation of arithmetic
spectra from free binary decision diagrams," in Proc. 30th IEEE Int.
Symp. on Circuits and Systems (ISCAS'97), Hong Kong, Vol 3, pp.
1764-1767, June 1997.
C13. B. J.
Falkowski and C. H. Chang, "Minimization
of partially-mixed-polarity Reed-Muller expansions for multiple output
incompletely specified Boolean functions," in Proc. 6th Workshop on
Post Binary Ultra-Large Scale Integration (WPBULSI'97), Antigonish, Nova
Scotia, Canada, pp. 45-46, May 1997.
C12. C. H. Chang and B. J. Falkowski,
"Operations on Boolean functions and variables in spectral domain of
arithmetic transform," in Proc. 29th IEEE Int. Symp. Circuits and
Systems (ISCAS'96), Atlanta, Georgia, USA, Vol. 4, pp. 400-403, May 1996.
C11. C. H. Chang and B. J. Falkowski,
"Flexible optimization of fixed polarity Reed-Muller expansions for
multiple output completely and incompletely specified Boolean
functions," in Proc. IEEE/IEICE Asia and South Pacific Design
Automation Conf. (ASP-DAC'95), Makuhari, Chiba, Japan, pp. 335-340,
August 1995.
C10.
B. J. Falkowski and C. H.
Chang, "Fast generalized arithmetic and adding transforms," in Proc.
8th IFIP WG10.5 Int. Conf. on Very Large Scale Integration (VLSI'95),
Makuhari, Chiba, Japan, pp. 723-728, August 1995. (Best paper award
candidate). C9.
B. J. Falkowski and C. H.
Chang, "Generation of multi-polarity arithmetic transform from
reduced representation of Boolean functions," in Proc. 28th IEEE Int.
Symp. on Circuits and Systems (ISCAS'95), Seattle, Washington, USA, pp.
2168-2171, May 1995.
C8.
B. J. Falkowski and C. H.
Chang "Efficient algorithms for the calculation of Walsh spectrum
from BDD and synthesis of BDD from Walsh spectrum for incompletely specified
Boolean functions", in Proc. 37th IEEE Midwest Symp. on Circuits and
Systems (MWSCAS'94), Lafayette, Louisiana, USA, pp. 393-396, August 1994. C7.
B. J. Falkowski and C. H.
Chang, "Efficient algorithms for the calculation of arithmetic
spectrum from OBDD and synthesis of OBDD from arithmetic spectrum for
incompletely specified Boolean functions", in Proc. 27th IEEE Int.
Symp. on Circuits and Systems (ISCAS'94), London, United Kingdom, vol. 1,
pp. 197-200, May 1994. C6.
B. J. Falkowski and C. H.
Chang, "Efficient algorithms for forward and inverse transformations
between Haar spectrum and binary decision diagram", in Proc. 13th
IEEE Int. Phoenix Conf. on Computers and Communications (IPCCC'94), Phoenix,
Arizona, USA, pp. 497-503, April. 1994. C5.
B. J. Falkowski and C. H.
Chang, "Generation of fixed polarity Reed-Muller expansions from
subset of Walsh spectral coefficients for completely specified Boolean
functions," in Proc. 5th Int. Workshop on Spectral Techniques (IWST'94),
Beijing, China, pp. 214-219, March 1994. C4.
B. J. Falkowski and C. H.
Chang, "A novel paired Haar based transform: algorithms and
interpretations in Boolean domain," in Proc. 36th IEEE
Midwest Symp. on Circuits and Systems (MWSCAS'93), Detroit, Michigan,
USA, pp. 1101-1104, August 1993. C3.
B. J. Falkowski, I. Schaefer
and C. H. Chang, "An efficient computer algorithm for the
calculation of disjoint cubes representation of Boolean functions", in Proc.
36th IEEE Midwest Symp. on Circuits and Systems (MWSCAS'93), Detroit,
Michigan, USA, pp. 1308-1311, August 1993. C2. M. A. Do, C. H. Chang
and J. T. Ong, "Implementation of randomised time division multiplexing
technique for automatic vehicle identification," in Proc. of the Int.
Conf. on Information Engineering (ICIE’91), Singapore, pp. 740-749 , December, 1991. C1.
M. A. Do, J. T. Ong, C. H.
Chang, T. H. Ooi, and D. Mital, "Automatic vehicle identification on
busy multi-lane city road," in Proc. of Vehicle Navigation &
Information Systems (VNIS'91), Dearborn, Michigon, USA, pp. 989-997 ,
1991.
Papers
in Local Journals and Technical Reports:
LJ5. X. Deng, P. Xu and C. H. Chang, "Self organizing topological tree for scheme color detection," EEE Research Bulletin, NTU, Singapore, January 2005. LJ4. Z. Ye, N. Nazimudeen and C. H. Chang, "Design of FIR filters with merged arithmetic architecture and delay-profile driven CPA," EEE Research Bulletin, NTU, Singapore, pp. 28-29, January 2004. LJ3. M. A. Do, K. S. Yeo, J. G. Ma, Y. P. Zhang, P. K. Chan, C. H. Chang and K. Y. See, "Software radio system-on-chip," EEE Research Bulletin, NTU, Singapore, pp. 2-5, January 2002. LJ2. J. Gu and C. H. Chang, "Multiplier based on redundant number representation in Booth encoded format," EEE Research Bulletin, NTU, Singapore, pp. 20-21, January 2002. LJ1. B. J. Falkowski and C. H. Chang, “Fast Generalized Arithmetic Transform,” Electrical and Electronic Engineering Research, ISSN 0218-2602, pp. 6-7, January 1997.
Papers
in Local Conferences:
LC9. J. Chen and C. H. Chang, “Design automation and optimization of FIR filters,” UK-Singapore Partners in Science – Microelectronics Embedded Systems Workshop (MES-2007), Singapore, 23-24 January 2007. LC8. A. Cui and C. H. Chang, “Research in digital watermarking for IP protection,” UK-Singapore Partners in Science – Microelectronics Embedded Systems Workshop (MES-2007), Singapore, 23-24 January 2007. LC7. R. K. Satzoda, C. H. Chang and T. Srikanthan, “Monte Carlo Statistical Analysis for Power Simulation in Synopsys Design Compiler,” Synopsys Users’ Group Conference, Singapore, Online publication, http://www.snug-universal.org/papers/papers.htm, Jun. 2006 LC6. S. Udit and C. H. Chang, "Modelling and simulation of fast multiplierless 2-D DCT architecture based on lifting scheme," Proceedings of the National Undergraduate Research Opportunity Program Congress (NUROP 2003), Singapore, September 2003. LC5. N. Naveen and C. H. Chang, "Synthesis of hardware efficient FIR filter coefficients," Proceedings of the National Undergraduate Research Opportunity Program Congress (NUROP 2003), Singapore, September 2003. LC3. X. Deng and C. H. Chang, "A review of potential image processing techniques for eyes tracking," Proceedings of the National Undergraduate Research Opportunity Program Congress (NUROP 2002), Singapore, September 2002. LC2. B. R. S. Putra and C. H. Chang, "Feasibility study of hybrid GMSK and pi/4 DQPSK receiver architecture," Proceedings of the National Undergraduate Research Opportunity Program Congress (NUROP 2002), Singapore, September 2002 LC1. S. M. Lee, F. L. Leong, S. Y. Tan, C. H. Chang and Y. Lian, “Static timing analysis: a systematic approach to stamp modeling of complex blocks,” Synopsys User Group Conference (SNUG 2001), Singapore, 1 June 2001. |
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