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Dr. Chip Hong CHANG
School of Electrical and Electronic Engineering
Nanyang Technological University

Blk S2, 50, Nanyang Avenue, Singapore 639798
Phone: +65 67905873; Fax: +65 67933318
E-mail: echchang@ntu.edu.sg


Research Interests:

Hardware Secruity and Trust, Residue Number Systems, Low-power Arithmetic Circuits, Digital Filter Design, Fault-tolerant Computing, Inexact Computing, Application-specific Digital Signal Processors, Neural Network Algorithms and Architectures.


"Meaningful life … is building your success towards significance.
  SUCCESS is when I add value to MYSELF,
  SIGNIFICANCE is when I add value to OTHERS."

Education

PDipTHE, Postgraduate Diploma for Teaching in Higher Education
National Institute of Education, Nanyang Technological University
2001
PhD, Spectral Techniques in Digital Logic Design
Nanyang Technological University, Singapore
1993 – 1997
MEng, A New Technique for Automatic Identification of Multiple Vechicles
Nanyang Technological University, Singapore
1990 – 1992
BEng, Honor, Electrical and Electronic Engineering
National University of Singapore, Singapore
1985 – 1989

Employment History

Tenure Associate Professor
Division of Circuits and Systems, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
2005 - Now
Assistant Professor
Division of Circuits and Systems, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
1999 - 2005
Project Consultant
Technical Application Division, Flextech Electronics Pte. Ltd., a fully owned subsidiary of a public listed company Flextech Holdings in Singapore
1998 - 1999
Lecturer
French-Singapore Institute (FSI), Nanyang Polytechnic, Singapore
1995 - 1998
Research Assistant
School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
1990 – 1995
Supplier Quality Engineer
General Motor Singapore Ltd
1989 – 1990

Concurrent Appointments

Assistant Chair of Alumni
School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore.
June 2008 - May 2014
Advisor and School Liaison of EEE Alumni Association.
Nanyang Technological University, Singapore
June 2008 - May 2014
Deputy Director
Centre of High Performance Embedded Systems the university level research centre hosted by the School of Computer Engineering and School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore.
February 2000 - December 2011
Program Director
VLSI Circuits and Embedded Systems Research Group, Centre of Integrated Circuits and Systems, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore.
April 2003 - December 2010
Chairman
School Search Committee for Three Assistant Professors in VLSI and IC Design
February 2009 – January 2010

Academic/Professional Honors and Awards:

2015 IEEE International Symposium on Circuits and Systems Finalist of the Best Student Paper Competition Award at Lisbon, Portugal on 25-27 May 2015
for the paper entitled “Public key protocol for usage-based licensing of FPGA IP cores” authored by Li Zhang and Chip-Hong Chang
Fellow, Institution of Engineering and Technology, 9 May 2007
The most senior category of membership awarded to members who have demonstrated significant individual responsibility, sustained achievement and exceptional professionalism during their careers
IEEE Senior Membership, 15 February 2003
Awarded by The Institute of Electrical and Electronics Engineers (IEEE) in recognition of experience reflecting professional maturity and significant professional achievements
Gold Leaf Certificate of the Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics 2010 (PrimeAsia 2010), 22-25 September 2010
The Gold Leaf Certificate was awarded to the paper entitled “A Very Low Power 0.7V Subthreshold Fully Programmable Gaussian Function Generator” authored by F. Li, C. H. Chang and L. Siek for demonstrating high quality research ranked in the first decile (top 10%) of the 103 papers presented at the conference.
Silver Leaf Certificate of the Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics 2010 (PrimeAsia 2010), 22-25 September 2010
The Silver Leaf Certificate was awarded to the paper entitled “Reduction of Partial Product Matrix for High-Speed Single or Multiple Constant Multiplication” authored by M. Faust and C. H. Chang for demonstrating high quality research ranked in the second decile (top 10-20%) of the 103 papers presented at the conference.
Student Travel Support Award and Finalist of Best Paper Award, IFIP International Conference on Very Large Scale Integration 1995 (VLSI ’95) International Conference Hall, Makuhari Messe, Chiba, Japan, August 29, 1995 – September 1, 1995.
Paper title: Fast Generalized Arithmetic and Adding Transform, coauthored with Dr. Bogdan J. Falkowski. (VLSI’95 is a biennial specialized VLSI conference in its ten year. It is held together with ASP-DAC’95 and CHDL’95.) 
Lista Innovation Prize 2005, 2nd prize, EMPA Academy, St. Gallen, Switzerland won by Mr. Urs Kuhn and Mr. Joerg Eugster.
(This accolade for outstanding innovative undergraduate project was awarded to Urs Kuhn and Joerg Eugster from the HSR University of Applied Sciences for their internship project titled "Truncated Multiplier in Digital Signal Processing" conducted in NTU under my supervision.) 
Collaboration Development Award from ReSMIQ, Canada, December 2007
Awarded by the Microsystems Strategic Alliance of Quebec, Canada for the research collaboration with Concordia University in Quebec.
Collaboration Development Award for Microelectronics and Embedded Systems, April 2007
Awarded by the Foregin and Commonwealth Office of British High Commission, Singapore under the Global Opportunities Fund for the research collaboration between scientists and engineers in the UK and SE Asia in the fields of Microelectronics and Embedded Systems
Oversea Attachment Programme (Outbound) Visiting Scholarship, June 2003
Awarded by the Agency for Science, Technology and Research (A*STAR) of Singapore to encourage university researchers for quality academic research collaborations with renowned overseas institutions. The OAP (Outbound) Committee award funding under this program on a competitive basis
Research Outcome Award Recognition (ROAR)
awarded by Nanyang Technological University, Office of Research in October 2006.
Research Outcome Award Recognition (ROAR)
awarded by Nanyang Technological University, Office of Research in February 2006.
Student Paper Contest for Financial Support to my PhD student, Ms. He Yajuan, Awarded by 2005 IEEE International Symposium on Circuits and Systems
Received 26 May 2005 by Ms. He Yajuan at International Conference Centre, Kobe, Japan (This financial support was awarded to 25 out of 148 outstanding student papers. My student, Ms. He Yajuan received this award for the following papers: Y. He, C. H. Chang, J. Gu and H. A. H. Fahmy, “A novel covalent redundant binary Booth encoder” and Y. He, C. H. Chang and J. Gu, “An area efficient 64-bit square root carry-select adder for low power applications”.)
2006 IEEE International Symposium on Circuits and Systems Student Travel Grant received by my PhD student, Ms. Yajuan He on 21 May 2006 at Kos Island, Greece
The travel grant was awarded to Ms. Yajuan He to present the paper: Y. He and C. H. Chang, “A low-power, high-speed RB-to-NB converter for fast redundant binary multiplier”
2006 IEEE International Symposium on Circuits and Systems Student Travel Grant received my PhD student, Ms. Aijiao Cui on 21 May 2006 at Kos Island, Greece
The travel grant was awarded to Ms. Aijiao Cui to present the paper: A. Cui and C. H. Chang, “Stego-signature at logic synthesis level for digital design IP protection”
2006 IEEE International Symposium on Circuits and Systems Student Travel Grant received by my PhD student, Mr. Jiajia Chen on 21 May 2006 at Kos Island, Greece
The travel grant of was awarded to Mr. Jiajia Chen to present the paper: C. H. Chang, J. Chen and A. P. Vinod, “Maximum likelihood disjunctive decomposition to reduced multirooted DAG for FIR filter design”
2008 IEEE International Symposium on Circuits and Systems Student Travel Grant received by my PhD student, Ms. Ramya Muralidharan on 19 May 2008 at the Sheraton Seattle Hotel, Seattle, Washington, USA
The travel grant was awarded to Ms. Ramya Muralidharan to present the paper: R. K. Satzoda, R. Muralidharan and C. H. Chang, “Programmable LSB-first and MSB-first modular multiplier for ECC in GF(2^m)”
2009 IEEE Circuits and Systems Singapore Chapter Graduate Student Award to my PhD student, Mr. Mathias Faust
received at the IEEE Circuits and Systems Singapore Chapter Graduate Student Workshop in Circuits, Systems and Signal Processing held on 29. September 2009. (The award carries with a certificate and a cash prize of S$200 was given to Mr. Mathias Faust for his outstanding academic performance and research contribution in Circuits, Systems and Signal Processing during his graduate study in Nanyang Technological University under my supervision and mentorship)
2010 IEEE International Symposium on Circuits and Systems Student Travel Grant received by my PhD student, Ms. Ramya Muralidharan on 1 June 2010 at Paris, France
The travel grant was awarded to Ms. Ramya Muralidharan to present the paper: R. Muralidharan and C. H. Chang, “Fast hard multiple generators for radix-8 Booth encoded modulo 2^n-1 and modulo 2^n+1 multipliers”
2010 IEEE International Symposium on Circuits and Systems Student Travel Grant received by my PhD student, Mr. Mathias Faust on 1 June 2010 at Paris, France
The travel grant was awarded to Mr. Faust Mathias to present the paper: M. Faust and C. H. Chang, “Minimal logic depth adder tree optimization for multiple constant multiplication”
2013 IEEE International Symposium on Circuits and Systems Student Travel Grant received by my PhD student, Mr. Jeremy Yung Shern Low on 20 May 2013 at the China National Convention Center, Bejing, China
The travel grant of was awarded to Mr. Jeremy Yung Shern Low to present the paper: J. Y. S. Low, T. H. Tay and C. H. Chang, “A signed integer programmable power-of-two scaler for {2^n-1, 2^n, 2^n+1} RNS”
Marquis Who’s Who in the World 2008-2009 - 25th silver anniversary special edition.
The biographical record inclusion is limited to those individuals who have demonstrated outstanding achievement in their own fields of endeavor and who have, thereby, contributed significantly to the betterment of contemporary society
Listed in Marquis Who’s Who in the World 2009-2013 Editions
Listed in Marquis Who’s Who in Science and Engineering 2011-2012 Edition
Listed in Marquis Who’s Who in Asia 2012 Edition
This biographical reference honors leading figures from the Asian region and this edition covers over 30,000 individuals from every significant field of endeavor including sciences, finance and business, government and politics, sports, entertainments and more.
Listed in 2010, 2011 Dictionary of International Biography – 35th and 36th Edition
AcademicKey’s Who’s Who in Engineering Education, 2006.
Listed in 2000 Outstanding Intellectuals of the 21st Century in 2008/2010 by the Research Academy of IBC
This title is published by the International Biographical Centre, Cambridge, England. Entry into this book is based on merit alone and editorial invitation.
Charter Fellow of Advisory Directorate International appointed by American Biographical Institute, Inc. (ABI) in July 2008
The appointment of Charter Fellow is to foster the leaders inspiring leaders goal of ABI by acknowledging the meaningful contributions and influence of an elite group of selected individuals
Vista Research Society of Industry Leaders (SIL), Invited Membership, 2006.

Research Grants

1. Principal co-investigator of “Sparse-represented Non-volatile In-memory Accelerator for Big-Data Analytics”, Ministry of Education Academic Research Grant Tier II August 2015, Project No. MOE2015-T2-2-013, Approved amount S$809,860.38, Target Date of Commencement: 1 July 2016. Target Date of Completion: 30 June 2019.
2. Principal Investigator of “Public Physical Unclonable Function for Secure Field Programmable Gate Array Intellectual Property Core Licensing and Configuration”, Ministry of Education Academic Research Grant Tier I September 2014, Project No. MOE2014-T1-002-141 (ARC 6/14), Approved amount S$150,000.00, Target Date of Commencement: 1 March 2015. Target Date of Completion: 28 February 2017.
3. Principal Investigator of “Ultra Low Power Neuromorphic Computing with Spin-devices”, Ministry of Education Academic Research Grant Tier II August 2012, Project No. MOE2013-T2-2-017 (ARC 6/14), Approved amount S$825,513.00, Target Date of Commencement: 16 June 2014. Target Date of Completion: 15 June 2017.
4. Collaborator of “Fine-grain Dynamically Reconfigurable Platform for High-performance Computing”, Ministry of Education Academic Research Grant Tier II August 2012, Project No. MOE2012-T2-1-126 (ARC 36/12), Approved amount S$651,176.00, Target Date of Commencement: 1 January 2013. Target Date of Completion: 31 December 2015.
5. Principal investigator of “Ultra Low Power Neuromorphic/Non-Boolean Computing with Spin Devices”, EEE Seed Research Grant 2013, Project No. 10002. Approved amount: S$50,000, Target Date of Commencement: 1 April 2013, Target Date of Completion: 31 March 2014.
6. Principal Singapore Collaborator of ‘Electronic Circuit Design – Systems’ team of Singapore-MIT Alliance for Research & Technology (SMART) 5-year Interdisciplinary Research Group (IRG5) research program on Low Energy Electronic Systems (LEES), Approved total program funding S$25M, target start date: January 2012. Target Date of Completion: December 2016. (The objective of LEES is to create an interdisciplinary research environment in which materials, device, and integrated researchers work together to shape innovation in seminconductor and integrated technology, leading to new low-energy systems. The goal of the ‘Electronic Circuit Design’ subprogram of LEES is to design the world’s first monolithic III-V/Si CMOS electronic and optoelectronic circuits and explore unique circuit designs that could not have been done with a silicon CMOS platform alone)
7. Principal co-investigator of “A 3D Design Platform of Multi-Processor System-on-Chip for New Media Application”, Ministry of Education Academic Research Grant Tier II August 2010, Project No. MOE2010-T2-2-037 (ARC 5/11), Approved amount S$857,125.00, Target Date of Commencement: 1 June 2011. Target Date of Completion: 31 May 2014.
8. Collaborator of “Application of watermarking techniques in VLSI IP protection", Project No. JC200903180629A, Shenzhen Bureau of Science, Technology and Information, Approved funding RMB100,000.00, Date of Acceptance: 1 March 2009. Target Date of Completion: 31 March 2010
9. Principal co-investigator of “Low Complexity Dynamically Reconfigurable Signal Processing for Cognitive Radio”, Project No. T208B1216 (ARC 10/08), Approved funding S$687,520.00, Date of Acceptance: 1 November 2008. Target Date of Completion: 31 October 2011.
10. Principal investigator of “Logical Reversibility and Redundancy for Dependable Nanoelectronic Computations”, F&E Phase II Funding, M8008.U.EEE.01, Approved amount S$43,715, Date of Acceptance: 1 November 2006. Date of Completion: 31 October 2007.
11. Collaborator of “A powerful datapath with less power?”, NTU College of Engineering Startup grant, M58020001.706022. Amount: S$98,000.
12. Principal co-investigator of “Low power reconfigurable receiver architectures for migrating software defined radio technology from base stations to handsets”, URC/AcRF (RG 8/05), Approved amount S$64,514, Date of Acceptance: 11 October 2005. Date of Completion: 31 December 2008
13. Principal co-investigator of “Power Sensitive Techniques for High Productivity Embedded Systems”, funded by A*STAR, Project No. 022 160 0046, Approved amount S$561,090. Date of Acceptance: April 2003. Date of Completion: 30 June 2006.
14. Principal investigator of “Algorithms and architectures for high rate WPAN”, Joint R&D between Panasonic Singapore Laboratory and NTU, MOU approved on 3 April 2001, total external funding of S$100,000 under research account number M48900001, Date of completion: 2 April 2004
15. Principal co-investigator of “Intelligent Embedded Systems”, ACRF (RG41/97), Approved amount S$99, 190, Date of Acceptance: 1 April 1998, Date of Completion: November 2001.

Editorship:

17. Guest Editor, Special Issue on “Emerging Attacks and Solutions for Secure Hardware in the Internet of Things”, IEEE Transaction on Dependable and Secure Computing, 2017.
16. Associate Editor, Springer Journal of Hardware and System Security (HASS), July 2016 – June 2019.
15. Associate Editor, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), January 2016-December 2017.
14. Associate Editor, IEEE Transactions on Information Forensic and Security (TIFS), 15 January 2016-15 January 2019.
13. International Advisory Committee, Jordan Journal of Computers and Information Technology, a new peer-review journal established by the Scientific Research Fund of Jordan, since March 2015.
12. Associate Editor, Microelectronics Journal, Published by Elsevier, Since June 2014.
11. Associate Editor, IEEE Access, since March 2013. IEEE Access is the IEEE’s first open access megajournal inaugurated in March 2013.
10. Associate Editor, Integration, the VLSI Journal, 2013-2015, published by Elsevier.
9. Associate Editor, IEEE Transactions on Circuits and Systems-I: Regular Papers, 2010 – 2011 and 2012 – 2013.
8. Associate Editor, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Since January 2011.
7. Editorial Board Member, Journal of Electrical and Computer Engineering, Hindawi Publishing Corporation, 2008-2014.
6. Editorial Advisory Board Member, The Open Electrial and Electronic Engineering Journal (OEEE), Bentham Science Publisher, 2007-2013.
5. Lead ‪Guest Editor, Special Issue on Convergence of Integrated Circuits and Complexity for the Journal of Circuits, Systems and Computers, vol. 25, no. 1, January 2016, published by World Scientific.
4. Guest Editor, Special Section on "2011 IEEE Custom Integrated Circuits Conference (CICC 2011)", IEEE Transacions on Circuits and Systems-I: Regular Papers, vol. 59, no. 8, August 2012.
3. Guest Editor, Special Issue on “Design and Automation for Integrated Circuits and Systems”, Journal of Electrical and Computer Engineering, June 2012, published by Hindawi Publishing Corporation.
2. Guest Editor, Special Issue on “Energy and Variability Aware Circuits and Systems”, Journal of Circuits, Systems and Computers, vol. 21, no. 8, 2012, published by World Scientific.
1. Guest Editor, Special Issue on “Green Integrated Circuits and Systems”, Journal of Circuits, Systems and Computers, vol. 20, no. 1, February 2011, published by World Scientific.

Organizing and Technical Program Committee
in International Conferences:

56. Proposer, Steering Committee and Program Committee, 1st Workshop on Attacks and Solutions in Hardware Security (ASHES), in conjunction and part of ACM Conference on Computer and Communications Security (CCS 2017), Dallas, USA, October 30 – November 3, 2017.
55. General Co-Chair, 14th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2018), Chengdu, China, 2018.
54. Track Chair, TC01: Security and Privacy of CE Hardware & Software Systems (SPC), 36th IEEE International Conference on Consumer Electronics (ICCE 2018), Las Vegas, USA, January 12-15, 2018.
53. Technical Program Committee, 25th IFIP/IEEE International Conference on Very Large Scale Integrtion (VLSI-SoC 2017), Abu Dhabi, UAE, October 23-25, 2017.
52. Technical Program Co-Chair, 2017 IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2017), Xiamen, China, November, 6-9, 2017.
51. International Advisory Committee, International Researcher Club Science, Engineering and Technology Conference (IRC-SET), Singapore, August 10-11, 2017.
50. International Scientific Committee, 2017 International Workshop on Advanced Algorithms and Control Engineering (IWAACE 2017), Bangkok, Thailand, March 10-12, 2017.
49. Technical Program Committee, 22nd IEEE Asia and South Pacific Design Automation Conference Computing (ASP-DAC 2017), Jan 16-19, Chiba/Tokyo, Japan.
48. Technical Program Committee, 22nd IEEE International Conference on Digital Signal Processing (DSP 2017), October 23-25, 2017, London, UK.
47. Publication Chair, 1st IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST-2016), December 19-20, Taipei, Taiwan.
46. General Vice-Chair, 13th International SoC Design Conference (ISOCC-2016), Jeju, Korea, October 23-26, 2016.
45. International Liaison, the XXXI IEEE Design of Circuits and Integrated Systems Conference (DCIS 2016), November, 23rd-25th, Granada, Spain.
44. Technical Program Committee, 21st IEEE International Conference on Digital Signal Processing (DSP 2016), October 16-18, Beijing, China.
43. Technical Program Committee, International Conference on Pervasive and Embedded Computing (PEC 2016), July 25-27, Lisbon, Portugal.
42. Advisor, 15th IEEE International Symposium on Integrated Circuits (ISIC 2016), Resort World Sentosa, Singapore, 12-14 December 2016.
41. International Advisory Committee, International Researcher Club Science, Engineering and Technology Conference (IRC-SET), Singapore, May 16, 2016.
40. Technical Program Committee, 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST 2016), McLean, Virginia, USA, May 3-5, 2016.
39. Special Session Organizer, “Emerging Hardware Security Threats and Countermeasures in the IoT Era”, 2016 IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montreal, Canada, May 22-25, 2016.
38. Review Committee Member, 2016 IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montreal, Canada, May 22-25, 2016.
37. Special Session Organizer, “Embedded Security and Trustable Integrated Circuits, Systems and Infrastructures”, 2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal, May 24-27, 2015.
36. Review Committee Member, 2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal, May 24-27, 2015.
35. Technical Program Committee, 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST 2015), Washington DC, USA, May 5-7, 2015.
34. Area Chair, Design and Implementaion of Signal Processing Systems, 23rd European Signal Processing Conference (EUSIPCO 2015), Nice, France, August 31 - September 4, 2015.
33. Technical Program Committee, 1st IEEE International Conference on VLSI Systems, Architecutres, Technology and Applications (VLSI-VATA 2015), Amrita Vishwa Vidyapeetham Bengaluru Campus,January 8-10, 2015.
32. Technical Program (Posters) Committee, 15th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid 2015), Shenzhen, China, May 4-7, 2015.
31. International Advisory Committee, 2015 IEEE Jordan Conference on Applied Electrical Engineering and Computing Technologies (AEECT 2015), The Dead Sea, Jordan, November 3-5, 2015.
30. Technical Program Co-Chair, International Researcher Club Science, Engineering and Technology Conference (IRC-SET 2015), National University of Singapore, Singapore, May 13, 2015.
29. International Advisory Board Member, 2nd IEEE International Conference on Electronics and Communication Systems (ICECS 2015), India, 26-27 February 2015.
28. General Chair, 14th IEEE International Symposium on Integrated Circuits (ISIC 2014), Marina Bay Sands, Singapore, December 10-12, 2014.
27. Area Chair, Design and Implementaion of Signal Processing Systems, 22nd European Signal Processing Conference (EUSIPCO 2014), Lisbon, Portugal, September 1-5, 2014.
26. Review Committee Member, 2014 IEEE International Symposium on Circuits and Systems (ISCAS 2014), Melbourne, Australia, June 1-5, 2014.
25. Special Session Organizer, “C3L-L: Unconventional Number Systems for Application-specific Digital Signal Processors”, 4 June 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS 2014), Melbourne, Australia, June 1-5, 2014.
24. International Program Committee, 2014 4th IEEE Interdisciplinary Engineering Design Education Conference (IEDEC 2014), Santa Clara, California, USA, March 3, 2014.
23. International Program Committee, 5th IEEE Asia Symposium on Quality Electronic Design (ASQED 2013), Penang, Malaysia, August 26-28, 2013.
22. Special Session Organizer, “Special Session A3L-F: 3DIC Platform for Heterogeneous System-on-Chip Integration”, May 20, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS 2013), Beijing, China, May 19-23, 2013.
21. Review Committee Member, 2013 IEEE International Symposium on Circuits and Systems (ISCAS 2013), Beijing, China, May 19-23, 2013.
20. International Program Committee, 17th IEEE CSI International Symposium on Computer Architecture & Digital Systems (CADS 2013), October 30-31, 2013, Tehran, Iran.
19. Technical Committee, IEEE Circuits and Systems Society VLSI Systems and Application, since May 2012.
18. Technical Program Committee, IEEE Region 10 Conference (TENCON 2012), Cebu, Philippines, November 19-22, 2012.
17. International Program Committee, 4th IEEE Asia Symposium on Quality Electronic Design (ASQED 2012), Penang, Malaysia, July 10-11, 2012.
16. International Program Committee, 3rd IEEE Asia Symposium on Quality Electronic Design (ASQED 2011), Kuala Lumpur, Malaysia, July 19-20, 2011.
15. Program Chair, 2010 International Conference on High-Speed Circuits Design (HSCD 2010), National Chin-Yi University of Technology, Taichung, Taiwan, 28-29 October 2010.
14. International Program Committee, 2nd IEEE Asia Symposium on Quality Electronic Design (ASQED 2010), Penang, Malaysia, August 3-4, 2010.
13. International Advisory Committee, 1st International Conference on Emerging Trends in Signal Processing and VLSI Design (SPVL-2010), GNEC Convention Center, Hyderabad, India, June 11-13, 2010.
12. Technical Advisory Committee, International Conference on VLSI Design & Communication Systems (ICVLSICOM-10), Chennai, India, January 8-10, 2010.
11. Special Session Chair, IEEE International Symposium on Integrated Circuits (ISIC 2009), Singapore, December 14-16, 2009.
10. International Program Committee, 2nd International Symposium on Intelligent Interactive Multimedia Systems and Services (KES-IIMSS-2009), University of Milan, Italy, July 15-16, 2009.
9. Technical Program Committee, 2007 IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2007), Xiamen, China, Nov 28 – December 1, 2007.
8. Technical Program Committee, 1st Workshop on System and Software in Wireless System-on-Chip (WSOC 2007), organized in conjunction with the 2007 IFIP International Conference on Embedded and Ubiquitous Computing, EUC 2007, Hsinchu, Taiwan, December 2007.
7. Review Committee Member, 11th IEEE International Symposium on Integrated Circuits (ISIC 2007), Singapore, September 26-28, 2007.
6. Organizing committee, UK-Singapore Partners in Science – Microelectronics Embedded Systems Workshop (MES-2007), Singapore, 23-24 January 2007.
5. Special Session Organizer, “Constraint-driven hardware for digital signal processing”, 2006 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS-2006), Singapore, December 4-6, 2006.
4. Publication Chair, 10th Asia Pacific Computer Systems Architecture Conference (ACSAC-2005), Singapore, October 24-26, 2005.
3. Technical Program Committee, 10th International Symposium on Integrated Circuits, Devices and Systems (ISIC 2004), Singapore, September 8-10, 2004.
2. Technical Program Committee, 9th International Symposium on Integrated Circuits, Devices and Systems, ISIC-2001, Singapore, September 3-5, 2001
1. Technical Program Committee, 8th International Symposium on Integrated Circuits, Devices and Systems, ISIC-1999, Singapore, September 8-10, 1999

Session Chair
of International Conferences:

22. Session Chair, “B1L-F: Hardware Security", 2017 IEEE International Symposium on Circuits and Systems (ISCAS 2017), Baltimore, USA, May 30, 2017.
21. Session Chair, “B3L-F: PUF Circuits & Hardware Trojans”, 2017 IEEE International Symposium on Circuits and Systems (ISCAS 2017), Baltimore, USA, May 30, 2017.
20. Session Chair, “GB-IV: Trust in Fabrication & Post-Silicon Adaptation for Hardware Security", 2017 IEEE International Symposium on Circuits and Systems (ISCAS 2017), Baltimore, USA, May 31, 2017.
19. Session Chair, “Session 7B: Hardware Diversity and Hardware Trojan”, 22nd IEEE Asia and South Pacific Design Automation Conference (ASP-DAC 2017), Chiba, Japan, January 19, 2017.
18. Session Chair, “Session 5: Hardware Platform Attack and Defense”, 1st IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST-2016), Taipei, Taiwan, December 19, 2016.
17. Session Chair, “B1L-B: VLSI Systems & Applications”, 2016 IEEE Asia Pacific Conference on Circuits and Systems, Jeju, Korea, October 27, 2016.
16. Session Chair, “Digital 2 – Digital Signal Processing Systems & Applications”, 2016 IEEE International SoC Design Conference (ISOCC 2016), Jeju, Korea, October 24 , 2016.
15. Session Chair, “Emerging Hardware Security Threats and Countermeasures in the IoT Era”, 2016 IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montreal, Canada, May 24, 2016.
14. Session Chair, “Embedded Security and Trustable Integrated Circuits, Systems and Infrastructures”, 2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal, 24-27 May 2015.
13. Session Chair, “C3L-L: Unconventional Number Systems for Application-specific Digital Signal Processors”, 2014 IEEE International Symposium on Circuits and Systems (ISCAS 2014), Melbourne, Australia, June 4, 2014.
12. Session Chair, “C8L-H: Memory Circuits and Architectures III”, 4 June 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS 2014), Melbourne, Australia, 1-5 June 2014.
11. Sesion Chair, “A3L-F: 3DIC Platform for Heterogeneous System-on-Chip Integration”, 20 May 2013, 2013 IEEE International Symposium on Circuits and Systems, Beijing, China, 2013.
10. Session Chair, “C2L-G: Programmable & Reconfigurable Architecture I”, 22 May 2013, 2013 IEEE International Symposium on Circuits and Systems, Beijing, China, 2013.
9. Session Chair, “Arithmetic Circuits”, 2006 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS-2006), Singapore, 6 December 2006.
8. Session Chair, “A3P-V: Novel Communication Techniques,” 2006 IEEE International Symposium on Circuits and Systems (ISCAS-2006), Kos, Greece, May 2006.
7. Session Chair, “C4P-V: Wireless Systems III,” 2006 IEEE International Symposium on Circuits and Systems (ISCAS-2006), Kos, Greece, May 2006.
6. Session Chair, “Simulation and Performance Evaulation,” 10th Asia Pacific Computer Systems Architecture Conference (ACSAS-2005), Singapore, 24-26 October 2005.
5. Session Chair, “Communication Circuits and Systems II,” 2005 IEEE International Symposium on Circuits and Systems (ISCAS-2005), Kobe, Japan, 26 May 2005.
4. Session Chair, “Computation Kernels and IP for Communication Systems - II,” 2004 IEEE International Symposium on Circuits and Systems (ISCAS-2004), Vancouver, Canada, 23-26 May 2004.
3. Session Chair, “Computer Network,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS-2002), Singapore, 17 December 2002.
2. Session Chair, “Image Manipulation and Compression I,” IASTED International Conference on Visualization, Imaging and Image Processing (VIIP-2002), Malaga, Spain, 9-12 September 2002.
1. Session Chair, “Image Manipulation and Compression II,” IASTED International Conference on Visualization, Imaging and Image Processing (VIIP-2002), Malaga, Spain, 9-12 September 2002.

Seminars and Professional Development Courses:

35. Silicon Physical Unclonable Functions: A Retrospective and A Look Forward, Invited seminar at the College of Electronic Science and Engineering, Shenzhen University, China, 9:00 a.m. to 12:00 noon, July 13, 2017.
34. Silicon Physical Unclonable Functions: A Retrospective and A Look Forward, Invited seminar at Room A601, organized by Center for Automative Electronics, Shenzhen Institute of Advanced Integration Technology, Shenzhen Institutes of Advanced Technology, Chinese Academic of Sciences, China, 2:00 p.m. to 4:30 pm, July 14, 2017.
33. Silicon Physical Unclonable Functions: A Retrospective and A Look Forward, Invited Seminar Microelectronics and Solid-state Electronics, Room A406, Harbin Institute of Technology Shenzhen Graudate School, China, 9:00 a.m. to 11:30 a.m., July 17, 2017.
32. Silicon Physical Unclonable Functions: Past, Up-to-date, and Future, Half-day Tutorial at the 2017 IEEE International Symposium on Circuits and Systems (ISCAS-2017), May 28, 2017, Maltimore, MD, USA.
31. The Emergence of Hardware-Oriented Security and Trust, Half-day Tutorial at 22nd IEEE Asia and South Pacific Design Automation Conference (ASP-DAC 2017), January 16, 2017, Chiba/Tokyo, Japan.
30. The Emergence of Hardware Security – A New Battlefield, lnvited seminar at School of Electronic Engineering, City University of Hong Kong, G6315, Academic 1, 11:00 a.m. – 12:00 noon, September 1, 2016.
29. The Emergence of Hardware Security – A New Battlefield, lnvited seminar at Department of Electrical and Computer Engineering, Hong Kong University of Science and Technology, Classroom 2406, 10:30 a.m.–11:30 a.m., August 31, 2016.
28. Hardware Integrity Protection – from IP Watermarking to Device Fingerprinting, Special seminar at Carnegie Mellon University, HH1107, 2:30 p.m., May 27, 2016.
27. Hardware Integrity Protection – from IP Watermarking to Device Fingerprinting, Invited seminar at University of Pittsburgh, 11:00 a.m., May 27, 2016.
26. Multi-valued Arbiters for Quality Enhancement of PUF Responses on FPGA Implementation, Invited lecture for Special Session on Cyber-Physical Systems and Security, 21st IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC 2016), Macao, China, 28 January 2016.
25. Scaling-assisted Sign Detection in Three-moduli Set Residue Number System, Invited Talk at the IEEE 11th International Conference on ASIC (ASICON 2015), November 5, 2015, Chengdu, China.
24. Fighting Counterfeiting – From Hardware IP Protection To Device Authentication, Invited speech at University of Electronic Science and Technology of China (UESTC), November 2015.
23. Fighting Counterfeiting – From Hardware IP Protection To Device Authentication, Invited speech at Singapore University of Technology and Design, 22 June 2015.
22. Hardware Security: Challenges, Solutions and Opportunities, Invited speech at Electrical and Computer Engineering (ECE) Department at Instituto Superior Técnico (IST), Technical University of Lisbon (UTL), Portugal, 27 May 2015.
21. Hardware Security: Challenges, Solutions and Opportunities, Keynote speech at the 1st International Researcher Club Science, Engineering and Technology Conference (IRC-SET), National University of Singapore, Singapore, 13 May 2015.
20. Authentication of Integrated Circuit Intellectual Property Against Piracy and Counterfeiting, Keynote speech at the 2013 Conference of Innovative Electronics Design and Applications (IED2013), 13 December 2013, National Chin-Yi University of Technology, Taichung, Taiwan. This conference is hosted by The Education Consortium of Innovative Electronics Design and Applications (IED) in Taiwan.
19. IQ, EQ and AQ – The Art of Well-being, Invited seminar at Ngee Ann Polytechnic, LT22, 21 November 2011.
18. NTU-TUM (Technische Universitat Műnchen) Joint MSc. Course on Integrated Circuit Design, 15 hours of lecture on “Digital Integrated Circuits”, 13-19 November 2013, 6-12 November 2012, 24 October-1 November 2011, 18-24 November 2010, 16-20 November 2009, 3-7 November 2008, 20-25 November 2007, 13-18 November 2006, 21-25 November 2005.
17. Invisible Watermarking for Integrated Circuit Intellectual Property Protection, Keynote speech at the World Congress on Science, Engineering and Technology 2009 (WCSET’09), River View Hotel, Singapore, 26 August 2009, organized by the World Academy of Science, Engineering and Technology (WASET).
16. Information Theoretic Approach to Multiple Constant Multiplications, Invited seminar presented at National Chiao Tung University, Hsinchu, Taiwan, 8 June 2009.
15. Common Subexpression Elimination for Design of Low Complexity FIR Filter, Invited seminar at the 1st International Workshop on Circuits and Systems Optimizations and Implementations, Nanyang Technological University, Singapore, 6 February 2009.
14. Staying Positive in a Tough Work Environment, Postgraduate student seminar at Beijing Jiaotong University, Beijing, China, 26 September 2008.
13. A Bumpy Road to Research Paper Publications, Seminar and dialogue session with students and academic staff at Beijing Jiaotong University, Beijing, China, 26 September 2008.
12. 低复杂度与高速有限脉冲响应滤波器的设计, Low Complexity and High-speed FIR Filter Design, Invited seminar (in Mandrain) presented at Beijing Jiaotong University, Beijing, China, 24 September 2008, invited by Beijing Jiaotong University.
11. Constraint based Watermarking for VLSI IP Protection, Invited seminar presented at Beijing Normal University, Beijing, China, 25 September 2008 under the auspicious of “Distinguished Lecturer Program” (“与大师面对面讲座”) of Beijing Normal University.
10. Digital Watermarking for IP Protection, Seminar presented at Concordia University, Montreal, Canada, 9 January 2008, Invited by ReSMIQ (The Microsystems Strategic Alliance of Quebec).
9. The Effort that Counts – An Insight into High-Speed CMOS Design, half-day graduate student course conducted at Concordia University, Montreal, Canada, 11 January 2008, Invited by ReSMIQ (The Microsystems Strategic Alliance of Quebec).
8. Computational Transformation for Low Complexity FIR Filter Design, Seminar presented at Surrey Space Center, University of Surrey, Guildford, United Kingdom, 12 July 2007.
7. Low Power and Redundant Binary Arithmetic Circuits for Digital Signal Processing, half day invited seminar presented at Harbin Institute of Technology, Harbin, China, on 4 December 2004.
6. On research publication – planning, preparation and review. Invited seminar and dialogue session with postgraduate students of Centre of Microelectonics, Harbin Institute of Technology, Harbin, China, on 5 December 2005.
5. Low Power, Low Voltage Arithmetic Circuits - From Basic Cells to Scalar Product Macrocell, at Edith Cowan University, Perth, Australia, 26 June 2003.
4. Efficient Reverse Converters for Residue Number Systems and Color Quantization by Self-organizing Map, at Edith Cowan University, Perth, Australia, 19 June 2003.
3. RF and Mixed Signal IC Design Course, Contracted by Institute of Microelectronics, Singapore (IME) to conduct a six-day practical training on the simualtion of high frequency circuits for their RTP (Reseach and Training Programme, A*STAR) trainees at the Nanyang Technological University, Singapore, 13-15, 20-22 January 2003.
2. Arithmetic Macrocell Design – From Algorithm to Architecture, at COE Technology Week focus siminar on Low Power Digital IC and DSP Design, held in Nanyang Technological University on 12 March 2002.
1. System-on-Chip for Wireless Communications, at National Science and Technology Board (NSTB) Workshop for Emerging Research in Embedded and Hybrid Systems, Singapore International Convention and Exhibition Center, on 7 August 2001.

Visiting Academic/Professorship:

1. Edith Cowan University, Perth, Australia, June 2003
2. Harbin Institute of Technology, China, December 2005
3. University of Surrey, Guildford, United Kingdom, July 2007
4. University of Westminster, London, United Kingdom, July 2007
5. Concordia University, Montreal, Canada, January 2008
6. Beijing Jiaotong University, Beijing, China, September 2008
7. University of Pittsburgh, Pittsburgh, USA, May 2016
8. Hong Kong University of Science and Technology, Hong Kong, August 2016

Memoranda of Understanding:

1.Research work led to the signing of memorandum of understanding on R & D collaboration (Algorithms and architectures for high rate WPAN) between Centre for High Performance Embedded Systems (Nanyang Technological University, Singapore) and the Panasonic Singapore Laboratory, Singapore, April 3, 2001.

Reviewer of International Journals and Conferences::

1.2014, 2015 Proceedings of the IEEE.
2.2015, ACM Transactions on Design Automation of Electronic Systems.
3.2002-2008, 2010-2015, IEEE Transactions on Circuits and Systems-I.
4.2003-2009, 2011-2015, IEEE Transactions on Circuits and Systems-II.
5.2005, 2009, 2010, 2014, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
6.2002, 2007, 2009-2012, 2014, 2015, IEEE Transactions on Computers.
7.2005, 2008, 2011, 2012, 2015, IEEE Transactions on Computer-Aided Design for Circuits and Systems.
8.2005-2008, 2010-2015, Journal of Circuits, Systems and Signal Processings.
9.2014, IEEE Transactions on Information Forensics and Security.
10.2014, IEEE Design & Test.
11.2014, IEEE Communications Letters.
12.2011, 2013, 2014, Microprocessors and Microsystems.
13.2014, The Arabian Journal for Science and Engineering.
14.2013, IEEE Transactions on Circuits and Systems for Video Technology.
15.2013, IEEE Transactions on Electron Devices.
16.2013, IEEE Transactions on Emerging Topics in Computing.
17.2013, Journal Foundations and Trends in Electronic Design Automation (FnTEDA).
18.2012, 2013, IET Proceedings - Computers and Digital Techniques.
19.2005, 2007-2013, Integration, the VLSI Journal.
20.2011, Microelectronics Journal.
21.2010, IEICE Electronics Express.
22.2009, IEEE Transactions on Audio, Speech and Language Processing.
23.2009, The Journal of Signal Processing Systems.
24.2009, Journal of Research and Practice in Information technology.
25.2008, 2011, 2012, The Open Electrical & Electronic Engineering Journal.
26.2007, 2008, IET Proceedings - Circuits, Devices and Systems.
27.2007, ASP Journal of Low Power Electronics.
28.2007, IEEE Transactions on Image Processings.
29.2001, 2002, 2005, 2007, IEE Proceedings - Computers and Digital Techniques.
30.2006, IEEE Transactions on Neural Networks.
31.2005, 2006, IEE Proceedings - Circuits, Devices and Systems.
32.2005, 2006, The Imaging Science Journal, official learned journal of Royal Photographic Society.
33.2005, Journal of Circuits Systems and Signal Processing, Special Issue on Computationally Efficient Digital Filter Design in Circuits, Systems and Signal Processing.
34.2002, 2003 EURASIP Journal of Applied Signal Processing.
35.2002, International Journal of Electronics.
36.2002, IEEE Transactions on Neural Networks, Special Issue on Authentication, Copyright Protection and Information.
37.2001, International Journal of Computers and Electrical Engineering.
38.2003-2015, IEEE International Symposium on Circuits and Systems (ISCAS).
39.2011, 9th IEEE International NEWCAS Conference (NEWCAS 2011), Special Session on Hardware-based Security, Bordeaux, France, 26-29 June, 2011.
40.2010, 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2010), Athens, Greece, 12-15 December 2010.
41.2010, 22nd IEEE International Conference on Microelectronics (ICM 2010), Cairo, Egypt, 19-22 December 2010.
42.2010, International Conference on VLSI Design & Communication Systems (ICVLSICOM-10), Chennai, India, 8-10 January, 2010.
43.2010, International Conference on Green Circuits and Systems (ICGCS-2010), Shanghai, China, 21-23 June, 2010.
44.2008, International Conference on VLSI Design (VLSI Design 2008), Hyderabad, India.
45.2007, International Workshop on Systems and Software for Wireless SoC (WSOC 2007), Taipei, Taiwan.
47.2007, IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2007), Xiamen, China.
48.2006, IEEE International Conference on Communications (ICC 2006) Istanbul, Turkey.
49.2004, IPSI-2004 Conference at Venice, Italy. 

Professional and Consultancy Services:

1. August 2013, Invited by Editor of World Scientific Publishing, Imperial College Press to review a new book proposal on Residue Number Systems and Applications.
2. October 2012, Invited by Assistant Editor of John Wiley and Sons, Ltd. England to review a new book proposal in 3D Vision.
3. October 2012, Invited to serve as international reviewer by The Austrian Science Fund FWF.
4. August 2012, Invited to serve as external reviewer by The Portuguese Foundation for Science and Technology (FCT).
5. August 2012, Invited to serve as a referee for Singapore Ministry of Education (MOE) Academic Research Fund (AcRF) Tier I research proposal.
6. March-December 2011, Act as advisor of a new start-up company Connaxion (www.connaxion.com). Connaxion explores new trend in internet to empower anyone to build and grow meaningful relationships by providing the tools to engage, manage and grow social network. With Connaxion, the website can be easily built and managed to make communities sustainable and profitable. Connaxion received the i.Jam funding and mentorship support by the Interactive Digital Media Program Office (IDMPO) of Singapore at SiTF Awards 2011.
7. February 2011, Invited by Associate Commissioning Editor of Engineering Technology of John Wiley and Sons, Ltd, UK to review a new book proposal on Circuit Mechanic.
8. June 2010, invited by the Senior Commissioning Editor of the Science and Technology Books of Elsevier South Asia to review of proposal and chapters of new book on VLSI System Design.
9. June 2008, Invited by the Research Co-ordinating Committee (RCC) of the Ministry of Education (MoE) Academic Research Fund (AcRF) Tier I to serve as a reviewer to appraise a completed research project.
10. June 2006 - contracted by Pearson Education South Asia Pte Ltd to carry out adaptation of the 4th Edition of the textbook “Digital Design: Principles and Practice” authored by John Wakerly.
11. Feb. 2006 – appointed as External Examiner for the Diploma in Electronic & Computer Engineering Course of the School of Engineering, Ngee Ann Polytechnic, Singapore for a period of four years from Academic Years 2006/2007 to 2010/2011.
12. May 2005, Invited by the Research Co-ordinating Committee (RCC) of the Ministry of Education (MoE) Academic Research Fund (AcRF) Tier I to serve as a reviewer to appraise a completed research project.
13. 1 January 2005 – 31 March 2005, Act as technical consultant to Panasonic Singapore Laboratory, providing suggestions and advises to analyze and evaluate power dissipation for their digital circuits and modules at RTL and gate level.
14. 1 Jul. 1999 – 30 Jun. 2000, Act as technical consultant to Flextech Electronics Pte. Ltd., a subsidiary company of a public listed Flextech Holdings, to provide suggestions and advises to Flextech Electronics technical application division, review findings and recommendations concerning the technologies, applications and expertise deemed suitable for the design and development of Flextech's project.
15. 1997, developed a new block cipher, Hash-based Iterative Data Encryption algorithm (HIDE), for Perfect Innovation Pte. Ltd., which specializes in fax routing devices and services. The symmetric cipher was designed based on an unbalanced Feistel structure with moderate speed and low memory requirement in order to be implemented directly on the resident 8-bit micro-controller of the fax router.

Click here for Google Scholar Citations

Theses and Dissertations:

T4. C. H. Chang, Electrical and Electronic Engineering Students’ Perspectives on Transferable Skill Acquisition. Postgraduate Diploma of Teaching in Higher Education Dissertation, National Institute of Education, March 2001.
T3. C. H. Chang, Spectral Techniques in Digital Logic. Ph.D. Thesis, School of Electrical and Electronic Engineering, Nanyang Technological University, October 1997.
T2. C. H. Chang, Deverlopment of A New Technique for Automatic Identification of Multiple Vehicles. M. Eng. Thesis, School of Electrical and Electronic Engineering, Nanyang Technological University, May 1992..
T1. C. H. Chang, High-gain Antennas for Teleview Reception. B. Eng. Final Year Report, School of Electrical and Electronic Engineering, Nanyang Technological Institute, National University of Singapore, February 1989.

Technology Disclosures and Patents:

P1. T. F. Tay and C. H. Chang, “Efficient Multiple Residue Error Detection and Correction Algorithm for Arithmetical Processing and Transmission in Residue Number System”, Patent Application No. 61/863,285, USA, Date filed: 07 August 2013.

Books and Book Chapters:

B4. H. Yu, C. H. Chang and A. Chattopadhyay, Emerging Technology and Architecture for Big-data Analytics, Springer International Publishing AG, Switzerland, May 2017.
B3. A. S. Molahosseini, L. Sousa and C. H. Chang, Embedded Systems Design with Special Arithmetic and Number Systems, Springer International Publishing AG, Switzerland, April 2017.
B2. C. H. Chang and M. Potkonjak (Ed.), Secure System Design and Trustable Computing. Springer International Publishing AG, Switzerland, October 2015.
B1. T. Srikanthan, J. Xue and C. H. Chang (Ed.), Advances in Computer Systems Architecture. Lecture Notes in Computer Science LNCS 3740, Springer-Verlag, Berlin, 2005.
BC10. J. Chen and C. H. Chang, “Double-base number system and its application in FIR filter design,” in Embedded Systems Design with Special Arithmetic and Number Systems, A. S. Molahosseini, L. Sousa and C. H. Chang, Ed., Springer International Publishing AG, Switzerland, pp. 277-310, April 2017.
BC9. T. F. Tay and C. H. Chang, “Fault-tolerant computing in redundant residue number systems,” in Embedded Systems Design with Special Arithmetic and Number Systems, A. S. Molahosseini, L. Sousa and C. H. Chang, Ed., Springer International Publishing AG, Switzerland, pp. 65-88, April 2017.
BC8. Y. He, J. Yang, and C. H. Chang, “Design and evaluation of Booth-encoded multipliers,” in Embedded Systems Design with Special Arithmetic and Number Systems, A. S. Molahosseini, L. Sousa and C. H. Chang, Ed., Springer International Publishing AG, Switzerland, pp. 113-147, April 2017.
BC7. C. H. Chang, M. Potkonjak and L. Zhang, “Hardware IP watermarking and fingerprinting,” in Secure System Design and Trustable Computing, C. H. Chang and M. Potkonjak Ed., Springer International Publishing AG, Switzerland, pp. 329–368, October 2015.
BC6. S. S. Zalivaka, L. Zhang, V. P. Klybik, A. A. Ivaniuk, and C. H. Chang, “Design and implementation of high quality PUF for hardware-oriented cryptography,” in Secure System Design and Trustable Computing, C. H. Chang and M. Potkonjak Ed., Springer International Publishing AG, Switzerland, pp. 39-81, October 2015.
BC5. L. Zhang and C. H. Chang, “Secure licensing of IP cores on SRAM-based FPGAs,” in Secure System Design and Trustable Computing, C. H. Chang and M. Potkonjak Ed., Springer International Publishing AG, Switzerland, pp. 391-418, October 2015.
BC4. P. K. Meher, C. H. Chang, O. Gustafsson, A. P. Vinod, and M. Faust, "Shift-add circuits for constant multiplications", in Arithmetic Circuits for DSP Applications, P. K. Meher and T. Stouraitis Ed., Wiley-IEEE Press, 2016.
BC3. C. H. Chang, M. Shibu and R. Xiao, "Self organizing feature map for color quantization on FPGA," in FPGA Implementations of Neural Networks, A. R. Omondi and J. C. Rajapakse, Ed., Chapter 8, pp. 225-245, Springer, The Netherlands, 2006.
BC2. R. K. Satzoda and C. H. Chang, “VLSI performance evaluation of systolic and semisystolic finite field multipliers,” in Advances in Computer Systems Architecture, Lecture Notes in Computer Science LNCS 3740, T. Srikanthan, J. Xue and C. H. Chang, Ed., pp. 693-706, Springer-Verlag, Berlin, 2005.
BC1. B. J. Falkowski and C. H. Chang, "Generation of fixed polarity Reed-Muller expansions from subset of Walsh spectral coefficients for completely specified Boolean functions," Invited Chapter, in "Advances in Spectral Techniques", C. Moraga, Ed., Special Issue of Book Series Berichte zur angewandten Informatik, (Reports on Applied Computer Science), pp. 21-26, University of Dortmund Publisher, Dortmund, Germany, 1998.

Papers in Refereed International Journals:

     
J92. C. Q. Liu, Y. Cao, and C. H. Chang, “A low-power, reliable and aging-resilient current starved inverted based ring oscillator physical unclonable function,” Special Issue on Selected Papers from 2017 CASS Regional Flagship Conferences, IEEE Transactions on Circuits and Systems–I: Regular Papers (Accepted in July 2017).
J91. S. Liu, J. Chen, C. H. Chang, and Y. Ai, “A new accurate and fast homography computation algorithm for sports and traffic video analysis,” IEEE Transactions on Circuits and Systems for Video Technology (Regular Paper, Accepted July 2017).
J90. J. Chen, C. H. Chang, J. Ding, R. Qiao, and M. Faust, “Tap delay-and-accumulate cost awarre coefficient synthesis algorithm for the design of area-power efficient FIR filters,” IEEE Transactions on Circuits and Systems–I: Regular Papers (Accepted in Jul. 2017).
J89. J. Chen, C. H. Chang, Y. Wang, J. Zhao and S. Rahardja, “New hardware and power efficient sporadic logarithmic shifters for DSP Applications,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (Transactions brief, Accepted July 2017).
J88. C. H. Chang, Y. Zheng, and L. Zhang, “A retrospective and a look forward: fifteen years of physical unclonable function advancement,” IEEE Circuits and Systems Magazine, to appear in 2017.
J87. J. Kwon, S. Goolaup, W. L. Gan, C. H. Chang, K. Roy, and W. S. Lew, “Asymmetrical domain wall propagation in bifurcated PMA wire structure due to the Dzyaloshinskii-Moriya interaction,” Applied Physis Letters (Accepted in May 2017).
J86. S. Kumar, C. H. Chang, and T. F. Tay, “New algorithm for signed integer comparison in {2^{n+k}, 2^n-1, 2^n+1, 2^{n+/-1}-1} and Its Efficient Hardware Implementation,” IEEE Transactions on Circuits and Systems–I: Regular Papers (Accepted, April 2016, DOI: 10.1109/TCSI.2016.2561718)
J85. J. Chen, J. Tan, C. H. Chang, and F. Feng, “A new cost-aware sensitivity-driven algorithm for the design of FIR filters,” IEEE Transactions on Circuits and Systems–I: Regular Papers (Accepted, April 2016, DOI: 10.1109/TCSI.2016.2557840)
J84. J. Kwon, S. Goolaup, F.N. Tan, C.H. Chang, K. Roy, and W.S. Lew, “Cyclic resistance change in perpendicularly magnetized Co/Ni nanowire induced by alternating current pulse injection,” Current Applied Physics, vol. 17, pp. 98-112, 2017.
J83. A. Cui, Y. Luo, and C. H. Chang, “Static and dynamic obfuscations of scan data against scan-based side-channel attacks,” IEEE Transactions on Information Forensics and Security vol. 12, no. 2, pp. 363-376, February 2017 (Regular Paper).
J82. Y. Wang, L. Ni, C. H. Chang and H. Yu, “DW-AES: A domain-wall nanowire based AES for high throughput and energy-efficient data encryption in non-volatile memory,” IEEE Transactions on Information Forensics and Security, vol. 11, no. 11, pp. 2426-2440, November 2016 (Regular Paper)
J81. J. Ding, J. Chen, and C. H. Chang, “A New Paradigm of Common Subexpression Elimination by Unification of Addition and Subtraction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 10, pp. 1605 – 1617, October 2016 (Regular Paper).
J80. C. H. Chang, C. Q. Liu, L. Zhang and Z. H. Kong, “Sizing of SRAM cell with voltage biasing techniques for reliability enhancement of memory and PUF functions,” Special Issue on Hardware Security – Threats and Countermeasures at the Circuit and Logic Levels, Journal of Low Power Electronics and Applications, vol. 6, no. 3, p. 16 (pp. 1-17), August 2016 (Invited Featured Article)
J79. S. Kumar and C. H. Chang, “A new fast and area-efficient adder-based sign detector for RNS {2^n-1, 2^n, 2^n+1},” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 7, pp. 2608-2612, July 2016 (Regular Paper).
J78. F. Feng, J. Chen, and C. H. Chang, “Hypergraph based minimum arborescence algorithm for the optimization and reoptimization of multiple constant multiplications,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 63, no. 2, pp. 233-244, Feb. 2016.
J77. T. F. Tay and C. H. Chang, "A non-iterative multiple residue digit error detection and correction algorithm in RRNS,” IEEE Transactions on Computers, vol. 65, no. 2, pp. 396-408, February 2016 (Regular paper).
J76. Y. Cao, L. Zhang, S. S. Zalivaka, C. H. Chang and S. Chen “CMOS image sensor based physical unclonable function for coherent sensor-level authentication,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 62, no. 11, pp. 2629-2640, November 2015.
J75. C. H. Chang, A. S. Molahosseini, A. A. E. Zarandi, and T. F. Tay, “Residue Number System - A new paradigm to datapath optimization for low-power and high-performance digital signal processing applications,” IEEE Circuits and Systems Magazine, vol. 15, no. 4, pp. 26-44, November 2015 (Feature paper).
J74. J. Kwon, S. Goolaup, G. J. Lim, I. S. Kerk, C. H. Chang, K. Roy, and W. S. Lew, “Low field domain wall dynamics in artificial spin-ice basis structure,” Journal of Appied Physics, vol. 118, no. 16, 163907, October 2015.
J73. T. F. Tay, C. H. Chang and L. Sousa, “Base transformation with injective residue mapping for dynamic range reduction in RNS,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 62, no. 9, pp. 2248-2259, September 2015.
J72. Y. Cao, L. Zhang, C. H. Chang, and S. S. Chen, “A low-power hybrid ring oscillator physical unclonable function with improved thermal stability for lightweight applications,” Special Section on Hardware Security and Trust, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 7, pp. 1143-1147, July 2015 (Regular paper).
J71. L. Zhang, X. Fong, C. H. Chang, Z. H. Kong, and K. Roy, “Optimizating emerging non-volatile memories for dual-mode applications: data storage and key generator,” Special Section on Hardware Security and Trust, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 7, pp. 1176-1187, July 2015 (Regular paper).
J70. L. Zhang, X. Fong, C. H. Chang, Z. H. Kong, and K. Roy, “Highly reliable spin-transfer torque magnetic RAM based physical unclonable function with multi-response-bits per cell,” IEEE Transactions on Information Forensics and Security, vol. 10, no. 8, pp. 1630-1642, August 2015 (Regular paper).
J69. A. Cui, L. Chen, and C. H. Chang, “Design of optimal scan tree based on compact test patterns for test time reduction,” IEEE Transactions on Computers, vol. 64, no. 12, pp. 3417-3429, Feb. 2015 (Regular paper).
J68. J. Chen, C. H. Chang, F. Feng, W. Ding and J. Ding, “Novel design algorithm for low complexity programmable FIR filters based on extended double base number system,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 62, no. 1, pp. 224-233, January 2015.
J67. Y. Cao, C. H. Chang and S. Chen, “A cluster-based distributed active current sensing circuit for hardware Trojan detection,” IEEE Transactions on Information Forensics and Security, vol. 9, no. 12, pp. 2220-2231, December 2014 (Regular Paper).
J66. L. Zhang and C. H. Chang, “A pragmatic per-device licensing scheme for hardware IP cores on SRAM based FPGAs,” IEEE Transactions on Information Forensics and Security, vol. 9, no. 11, pp. 1893-1905, November 2014 (Regular Paper).
J65. F. Li, C. H. Chang, A. Basu and L. Siek, “A 0.7 V low-power fully programmable Gaussian function generator for brain-inspired Gaussian correlation associative memory,” Special Issue on Brain Inspired Models of Cognitive Memory, Neurocomputing, vol. 138, pp. 69-77, August 2014 (Regular Paper).
J64. L. Zhang, Z. H. Kong, C. H. Chang, A. Cabrini, G. Torelli, “Exploiting process variations and programming sensitivity of phase change memory for reconfigurable physical unclonable functions,” IEEE Transactions on Information Forensics and Security, vol. 9, no. 6, pp. 921-932, June 2014 (Regular Paper).
J63. C. H. Chang and L. Zhang, “A blind dynamic fingerprinting technique for sequential circuit intellectual property protection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 1, pp. 76-89, January 2014 (Regular Paper)
J62. R. Muralidharan and C. H. Chang, “Radix-4 and radix-8 Booth encoded multi-modulus multipliers,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 60, no. 11, pp. 2940-2952, November 2013.
J61. T. F. Tay, C. H. Chang and J. Y. S. Low, “Efficient VLSI implementation of 2^n scaling of signed integer in RNS {2^n-1, 2^n, 2^n+1},” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 10, pp. 1936-1940, October 2013.
J60. J. Y. S. Low and C. H. Chang, “A new approach to the design of efficient residue generators for arbitrary moduli,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 60, no. 9, pp. 2366-2374, September 2013.
J59. H. Qian, C. H. Chang and H. Yu, “An efficient channel clustering and flow rate allocation algorithm for non-uniform microfluidic cooling of 3D integrated circuits,” Special Issue on Thermal Modeling and Simulation, Thermal-Aware Design, and Thermal Management for 2D/3D ICs, Integration, The VLSI Journal, vol. 46, no. 1, pp. 57-68, January 2013 (Regular Paper).
J58. F. Li, A. Basu, C. H. Chang and A. H. Cohen, “Dynamical systems guided design and analysis of silicon oscillators for central pattern generators,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 59, no. 12, pp. 3046-3059, December 2012.
J57. M. R. Meher, C. C. Jong and C. H. Chang, “An area and energy efficient inner-product processor for serial-link bus architecture,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 59, no. 12, pp. 2945-2955, December 2012.
J56. J. Y. S. Low and C. H. Chang, “A VLSI efficient programmable power-of-two scaler for {2^n-1, 2^n, 2^n+1} RNS,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 59, no. 12, pp. 2911-2919, December 2012.
J55. R. Muralidharan and C. H. Chang, “Area-power efficient modulo 2^n-1 and modulo 2^n+1 multipliers for {2^n-1, 2^n, 2^n+1} based RNS,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 59, no. 10, pp. 2263 – 2274, October 2012.
J54. R. Huang, C. H. Chang, M. Faust, N. Lotze and Y. Manoli, “Sign-extension avoidance and word-length opitmization by positive offset representation for FIR filter design,” IEEE Transactions on Circuits and Systems–II: Express Brief, vol. 58, no. 12, pp. 916-920, December 2011.
J53. C. H. Chang and J. Y. S. Low, “Simple, fast and exact RNS scaler for the three-moduli set {2^n-1, 2^n, 2^n+1},” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 58, no. 11, pp. 2686-2697, November 2011.
J52. M. R. Meher, C. C. Jong, C. H. Chang, “A high bit rate serial-serial multiplier with on-the-fly accumulation by asynchronous counters,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 10, pp. 1733-1745, October 2011 (Regular paper).
J51. R. Muralidharan and C. H. Chang, “Radix-8 Booth encoded modulo 2^n-1 multipliers with adaptive delay for high dynamic range residue number system,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 58, no. 5, pp. 982-993, May 2011.
J50. A. Cui, C. H. Chang, S. Tahar and A. A. Hamid, “A robust FSM watermarking scheme for IP protection of sequential circuit design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol 30, no. 5, pp. 678-690, May 2011 (Regular paper).
J49. Y. Shao and C. H. Chang, “Bayesian separation with sparsity promotion in perceptual wavelet domain for speech enhancement and hybrid speech recognition,” IEEE Transactions on Systems, Man and Cybernetics, Part A: Systems and Human, vol. 41, no. 2, pp. 284-293, March 2011 (Regular paper).
J48. H. Qian, X. Huang, H. Yu and C. H. Chang, “Cyber-physical Thermal Management of 3D Mult-core Cache Processor System with Microfluidic Cooling,”ASP Journal of Low Power Electronics, vol. 7, no. 1, pp. 110-121, February 2011 (Regular paper).
J47. M. Faust, O. Gustafsson and C. H. Chang, “Fast and VLSI efficient binary-to-CSD encoder using bypass signal,” IET Electronics Letters, vol. 47, no. 1, January 2011 (featured in the in-brief section of the issue).
J46. C. H. Chang and R. K. Satzoda, “A low error and high performance multiplexer-based truncated multiplier,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 12, pp. 1767-1771, December 2010.
J45. C. H. Chang and A. Cui, “Synthesis-for-testability watermarking for field authentication of VLSI intellectual property,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 57, no. 7, pp. 1618-1630, July 2010.
J44. C. H. Chang and M. Faust, “On ‘A new common subexpression elimination algorithm for realizing low-complexity higher order digital filters’,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 5, pp. 844-848, May 2010.
J43. J. Chen and C. H. Chang, “High-level synthesis algorithm for the design of reconfigurable constant multiplier,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 12, pp. 1844-1856, December 2009 (Regular Paper).
J42. Y. He and C. H. Chang, “A new redundant binary Booth encoding for fast 2^n-bit multiplier design,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 56, no. 6, pp. 1192-1201, June 2009.
J41. A. Cui, C. H. Chang and S. Tahar, “IP watermarking using incremental technology mapping at logic synthesis level,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 9, pp 1565-1570, September 2008 (Regular paper).
J40. C. H. Chang, J. Chen and A. P. Vinod, “Information theoretic approach to complexity reduction of FIR filter design,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 55, no. 8, pp. 2310-2321, September 2008.
J39. F. Xu, C. H. Chang and C. C. Jong, “Contention resolution – a new approach to versatile subexpressions sharing in multiple constant multiplications,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 55, no. 2, pp. 559 – 571, March 2008.
J38. Y. He and C. H. Chang, “A power-delay efficient hybrid carry-lookahead/carry-select based redundant binary to two's complement converter,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 55, no. 1, pp. 336-346, February 2008.
J37. F. Xu, C. H. Chang and C. C. Jong, “Design of low-complexity FIR filters based on signed-powers-of-two coefficients with reusable common subexpressions,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 10, pp. 1898-1907, October 2007.
J36. Y. Shao and C. H. Chang, “A generalized time-frequency subtraction method for robust speech enhancement based on Wavelet filter bank modeling of human auditory system,” IEEE Transactions on Systems, Man and Cybernetics, Part B: Cybernetics, vol. 37, no. 4, pp. 877- 889, August 2007 (Regular paper).
J35. B. Cao, C. H. Chang and T. Srikanthan, “A residue-to-binary converter for a new 5-moduli set,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol. 54, no. 5, pp. 1041-1049, May 2007.
J34. F. Xu, C. H. Chang and C. C. Jong, “Hamming weight pyramid – a new insight into canonical signed digit representation and its applications,” Journal of Computers and Electrical Engineering, vol. 33, no. 3, pp. 195-207, May 2007 (Regular Paper).
J33. A. P. Vinod, A. Singla and C. H. Chang, “Low power differential coefficients-based FIR filters using hardware optimized multipliers,” IEE Proceedings, Circuits, Devices and Systems, vol. 1, no. 1, pp. 13-22, February 2007 (Regular Paper).
J32. R. K. Satzoda, C. H. Chang and C. C. Jong, “High throughput and low complexity bit parallel and bit serial systolic architectures for Montgomery modular multiplication,” WSEAS Transactions on Circuits and Systems, vol. 5, no. 5, pp. 734-741, May 2006 (Invited Regular Paper).
J31. Z. H. Kong, K. S. Yeo and C. H. Chang, “An ultra low-power current-mode sense amplifier for SRAM applications,” Journal of Circuits, Systems and Computers, vol. 14, no. 5, pp. 939-951, October 2005 (Regular Paper).
J30. F. Xu, C. H. Chang and C. C. Jong, “Contention resolution algorithms for common subexpression elimination in digital filter design,” IEEE Transactions on Circuits and Systems-II Express Brief, vol. 52, no. 10, pp. 695-700, October 2005.
J29. B. Cao, T. Srikanthan and C. H. Chang, “Efficient reverse converters for the four-moduli sets {2^n-1, 2^n, 2^n+1, 2^(n+1)-1} and {2^n-1, 2^n, 2^n+1, 2^(n-1)-1},” IEE Proceedings, Computers and Digital Techniques, vol. 152, no. 5, pp. 687-696, September 2005 (Regular Paper).
J28. C. H. Chang, J. Gu and M. Zhang, “A review of 0.18um full adder performances for tree structured arithmetic circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 6, pp. 686-695, June 2005 (Regular Paper).
J27. P. Xu, C. H. Chang and A. Paplinski, “Self-organizing topological tree for online vector quantization and data clustering,” Special Issue on Learning in Computer Vision and Pattern Recognition, IEEE Transactions on Systems, Man and Cybernetics, Part B: Cybernetics, vol. 35, no. 3, pp. 515-526, June 2005 (Regular Paper).
J26. Z. H. Kong, K. S. Yeo and C. H. Chang, “Design of an area-efficient CMOS multiple-valued current comparator circuit,” IEE Proceedings, Circuits, Devices and Systems, vol. 152, no. 2, pp. 151-158, April 2005 (Regular Paper).
J25. F. Xu, C. H. Chang and C. C. Jong, “Modified reduced adder graph algorithm for multiplierless FIR filters,” IEE Electronics Letters, vol. 41, no. 6, pp. 302-303, March 2005.
J24. C. H. Chang, P. Xu, R. Xiao and T. Srikanthan, “New adaptive color quantization method based on self-organizing maps,” IEEE Transactions on Neural Networks, vol. 16, no. 1, pp. 237-249, January 2005 (Regular Paper).
J23. C. H. Chang, Z. Ye and M. Zhang, “Fuzzy-ART based adaptive digital watermarking scheme,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 1, pp. 65-81, January 2005 (Regular Paper).
J22. C. H. Chang, J. Gu and M. Zhang, “Ultra low voltage, low power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits,” IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 51, no. 10, pp. 1985-1997, October 2004.
J21. J. Gu, C. H. Chang and K. S. Yeo, “Algorithm and architecture of a high density, low power scalar product macrocell,” IEE Proceedings, Computers and Digital Techniques, vol. 151, no. 2, pp. 161-172, March 2004 (Regular Paper).
J20. B. Cao, C. H. Chang and T. Srikanthan, “An efficient reverse converter for the 4-moduli set {2^n-1, 2^n, 2^n+1, 2^(2n)+1} based on the New Chinese Remainder Theorem,” IEEE Transactions on Circuits and Systems–I: Fundamental Theory and Applications, vol. 50, no. 10, pp. 1296-1303, October 2003 (Regular paper)
J19. C. H. Chang, H. Tian, T. Srikanthan and C. S. Lim, “A FPGA based architecture for real time image segmentation by region growing algorithm,” Journal of Electronic Imaging, vol. 11, no. 4, pp. 469-478, October 2002 (Regular Paper).
J18. C. H. Chang and B. J. Falkowski, “Boolean matching filters based on row and column weights of Reed-Muller polarity coefficient matrix,” VLSI Design, An International Journal of Custom-Chip Design, Simulation and Testing, vol. 14, no. 3, pp. 259-271, May 2002 (Regular Paper).
J17. B. J. Falkowski and C. H. Chang, “Minimization of k-variable mixed-polarity Reed-Muller expansions,” VLSI Design, An International Journal of Custom-Chip Design, Simulation and Testing, vol. 11, no. 4, pp. 311-320, October 2000 (Regular Paper).
J16. B. J. Falkowski and C. H. Chang, “Generalized k-variable-mixed-polarity Reed-Muller expansions for systems of Boolean functions and their minimization,” IEE Proceedings, Circuits, Devices and Systems, vol. 147, no. 4, pp. 201-210, August 2000 (Regular Paper).
J15. B. J. Falkowski and C. H. Chang, “Paired Haar spectra computation through operations on disjoint cubes,” IEE Proceedings, Circuits, Devices and Systems, vol. 146, no. 3, pp. 117-123, June 1999 (Regular Paper).
J14. C. H. Chang and B. J. Falkowski, “NPN Classification using weight and literal vectors of Reed-Muller expansion,” IEE Electronics Letters, vol 35, no. 10, pp. 798-799, May 1999.
J13. B. J. Falkowski and C. H. Chang, “Efficient algorithm for the calculation of generalized Adding and Arithmetic transforms from disjoint cubes of Boolean functions,” VLSI Design, An International Journal of Custom-Chip Design, Simulation and Testing, vol. 9, no. 2, pp. 135-146, April 1999 (Regular Paper).
J12. B. J. Falkowski and C. H. Chang, “Hadamard-Walsh spectral characterization of Reed-Muller expansions,” Computers and Electrical Engineering, An International Journal, vol. 25, no. 2, pp. 111-134, March 1999 (Regular Paper).
J11. B. J. Falkowski and C. H. Chang, “Properties and calculation of Paired Haar transform,” Journal of Approximation Theory and Its Applications, vol. 15, no. 2, pp. 1-14, February 1999 (Regular Paper).
J10. C. H. Chang and B. J. Falkowski, “Haar spectra based entropy approach to quasi-minimisation of FBDDs,” IEE Proceedings, Computers and Digital Techniques, United Kingdom, vol. 146, no. 1, pp. 41-49, January 1999 (Regular Paper).
J9. C. H. Chang and B. J. Falkowski, “Adaptive exact optimization of Reed-Muller expansions for system of functions,” IEE Proceedings, Computers and Digital Techniques, vol. 145, no. 6, pp. 385-394, November 1998 (Regular Paper).
J8. C. H. Chang and B. J. Falkowski, “Logical manipulations and design of tributary network in Arithmetic spectral domain,” IEE Proceedings, Computers and Digital Techniques, vol. 145, no. 5, pp. 347-356, September 1998 (Regular Paper).
J7. B. J. Falkowski and C. H. Chang, “Mutual conversions between generalized Arithmetic expansions and free binary decision diagrams,” IEE Proceedings, Circuits, Devices and Systems, vol. 145, no. 4, pp. 219-228, August 1998 (Regular Paper).
J6. B. J. Falkowski and C. H. Chang, “Efficient calculation of Gray code ordered Walsh spectra through Algebraic Decision Diagram,” IEE Electronics Letters, vol. 34, no. 9, pp. 848-850, April 1998.
J5. B. J. Falkowski and C. H. Chang, “Forward and inverse transformations between Haar spectra and ordered binary decision diagrams of Boolean functions,” IEEE Transactions on Computers, vol. 46, no. 11, pp. 1272-1279, November 1997.
J4. C. H. Chang and B. J. Falkowski, “Efficient symbolic computation of generalized spectra,” IEE Electronics Letters, vol. 33, no. 22, pp. 1837-1838, October 1997.
J3. B. J. Falkowski and C. H. Chang, “Properties and methods of calculating generalized arithmetic and adding transforms,” IEE Proceedings, Circuits, Devices and Systems, vol. 144, no. 5, pp. 249-258, October 1997 (Regular Paper).
J2. B. J. Falkowski and C. H. Chang, “Exact minimizer of fixed polarity Reed-Muller expansions,” International Journal of Electronics, vol. 79, no. 4, pp. 389-409, October 1995 (Regular Paper).
J1. M. A. Do and C. H. Chang, “Design and performance of a new multi-lane AVI system,” Intelligent Vehicle Highway System (IVHS) Journal, vol 1, no. 2, pp. 151-166, 1993 (Regular Paper).

Papers in Refereed International Conferences:

                         
C159. Y. Zheng, Y. Cao, and C. H. Chang, “User device physical unclonable function for security management of bring your own device (BYOD),” Special Session on Architecture-Level Energy, Security, and Reliability Solutions for CE Digital Hardware, the 36th IEEE Int. Conf. on Consumer Electronics (ICCE 2018), Las Vegas, USA, January 12-14, 2018 (Invited paper).
C158. M. Potkonjak, G. Qu, F. Koushanfar and C. H. Chang, “20 years of research on intellectual property protection,” in Proc. 2017 IEEE Int. Symp. on Circuits and Systems (ISCAS-2017), Maltimore, MD, USA, May 28-31, 2017 (accepted).
C157. C. Q. Liu, Y. Zheng, and C. H. Chang, “A new write-contention based dual-port SRAM PUF with multiple response bits per cell,” in Proc. 2017 IEEE Int. Symp. on Circuits and Systems (ISCAS-2017), Maltimore, MD, USA, May 28-31, 2017 (accepted).
C156. S. S. Zalivaka, A. A. Ivaniuk, and C. H. Chang, “Low-cost fortification of arbiter PUF against modeling attack,” in Proc. 2017 IEEE Int. Symp. on Circuits and Systems (ISCAS-2017), Maltimore, MD, USA, May 28-31, 2017 (accepted).
C155. Z. Wang, A. Patil, A. Basu, and C. H. Chang, “Current mirror array: a novel lightweight strong PUF topology with enhanced reliability,” in Proc. 2017 IEEE Int. Symp. on Circuits and Systems (ISCAS-2017), Maltimore, MD, USA, May 28-31, 2017 (accepted).
C154. X. Huang, A. Cui, and C. H. Chang, “A new watermarking scheme on scan chain ordering for hard IP protection,” in Proc. 2017 IEEE Int. Symp. on Circuits and Systems (ISCAS-2017), Maltimore, MD, USA, May 28-31, 2017 (accepted).
C153. S. S. Zalivaka, A. A. Ivaniuk, and C. H. Chang, “FPGA implementation of modeling attack resistant arbiter PUF with enhanced reliability,” in Proc. 18th IEEE International Symposium on Quality Electronic Design (ISQED 2017), Special session on IoT Security: Protocol, Implementation and Attacks, Santa Clara, CA, USA, March 13-15, 2017 (Invited Paper).
C152. Y. Zheng, Y. Cao, and C. H. Chang, “A new event-driven dynamic vision sensor based physical unclonable function for camera authentication in reactive monitoring System,” in Proc. 1st IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST 2016), Yilan, Taiwan, 19-20 December 2016.
C151. Y. Cao, L. Zhang, and C. H. Chang, “Using image sensor PUF as root of trust for birthmarking of perceptual image hash,” in Proc. 1st IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST 2016), Yilan, Taiwan, 19-20 December 2016.
C150. S. Dhabu and C. H. Chang, “A new scheme for secret-hiding in DSP circuit,” in Proc. 13th International SoC Design Conference (ISOCC 2016), Jeju, Korea, pp. 49-50, 23-26 October, 2016.
C149. T. P. T. Ho and C. H. Chang, “Accelerating residue-to-binary conversion of very high cardinality moduli set for fully homomorphic encryption,” in Proc. 2016 IEEE Asia Pacific Conference on Circuits & Systems (APCCAS 2016), Jeju, Korea, pp. 9-12, 25-28 October, 2016.
C148. C. Q. Liu, Y. Cao and C. H. Chang, “Low-power, lightweight and reliability-enhanced current starved inverter based RO PUFs,” in Proc. 2016 IEEE Asia Pacific Conference on Circuits & Systems (APCCAS 2016), Jeju, Korea, pp. 646-649, 25-28 October, 2016.
C147. G. Narasimman, S. Roy, X. Fong, K. Roy, C. H. Chang, and A. Basu “A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks,” in Proc. 2016 IEEE Int. Symp. on Circuits and Systems (ISCAS-2016), Montreal, Canada, pp. 914-917, 22-26 May 2016.
C147. G. Narasimman, S. Roy, X. Fong, K. Roy, C. H. Chang, and A. Basu “A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks,” in Proc. 2016 IEEE Int. Symp. on Circuits and Systems (ISCAS-2016), Montreal, Canada, pp. 914-917, 22-26 May 2016.
C146. S. Kumar and C. H. Chang, “A VLSI-efficient signed magnitude comparator for {2^n-1, 2^n, 2^{n+1}-1} RNS,” in Proc. 2016 IEEE Int. Symp. on Circuits and Systems (ISCAS-2016), Montreal, Canada, pp. 1966- 1969, 22-26 May 2016.
C145. J. Kwon, H. K. Teoh, S. Goolaup, G. J. Lim, W. Gan, C. H. Chang, K. Roy, and W. S. Lew, "Chirality-dependent domain wall pinning and oscillation at Ta hall probe in perpendicular magnetic anisotropy nanowires" 2016 Joint MMM-Intermag Conference, San Diego, USA, pp. 961, Jan. 2016.
C144. J. Kwon, S. Goolaup, G. J. Lim, W. Gan, C. H. Chang, K. Roy, and W. S. Lew, "Spin-Hall torque induced domain wall motion in PMA nanowire network" 2016 Joint MMM-Intermag Conference, San Diego, USA, pp. 901, Jan. 2016.
C143. S. S. Zalivaka1, A. V. Puchkov, V. P. Klybik, A. A. Ivaniuk, and C. H. Chang, “Multi-valued arbiters for quality enhancement of PUF responses on FPGA implementation,” Special Session on Cyber-Physical Systems and Security, in Proc. 21st IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC 2016), Macao, China, pp. 533-538, 26-28 Jan. 2016 (Invited Paper).
C142. S. Kumar and C. H. Chang, “A high-speed and area-efficient sign detector for three moduli set RNS {2^n, 2^n−1, 2^n+1},” in Proc. 2015 IEEE 11th Int. Conf. on ASIC (ASICON 2015), China, Chengdu, B3-1, pp. 1-4, 3-6 Nov. 2015 (Invited Paper).
C141. M. Faust, M. Kumm, C. H. Chang, and P. Zipf, “Efficient structural adder pipelining in transposed form FIR filters,” in Proc. 2015 IEEE Int. Conf. on Digital Signal Processing (DSP-2015), Singapore, pp. 311-314, 21-24 July 2015.
C140. J. Kwon, I. Kerk, G. Lim, C. Murapaka, S. Goolaup, C. H. Chang, and W. Lew, “Metastable magnetic domain in bifurcated nanowire network probed by domain wall magnetoresistance,” in Proc. 2015 IEEE Int. Magnetics Conf. (INTERMAG 2015), China, Beijing, 11-15 May 2015, Session HB-10, Domain Wall Motion and Logic Devices, pp. 263.
C139. T. F. Tay and C. H. Chang, “A new unified modular adder/subtractor for abitrary moduli,” in Proc. 2015 IEEE Int. Symp. on Circuits and Systems (ISCAS-2015), Lisbon, Portugal, pp. 53-56, 24-27 May 2015.
C138. L. Zhang and C. H. Chang, “Public key protocol for usage-based licensing of FPGA IP cores,” in Proc. 2015 IEEE Int. Symp. on Circuits and Systems (ISCAS-2015), Lisbon, Portugal, pp. 25-28, 24-27 May 2015.
C137. L. Zhang, C. Liu and C. H. Chang, “Statistical analysis and design of 6T SRAM cell for physical unclonable function with dual application modes,” in Proc. 2015 IEEE Int. Symp. on Circuits and Systems (ISCAS-2015), Lisbon, Portugal, pp. 1410-1413, 24-27 May 2015.
C136. Y. Cao, S. S. Zalivaka, L. Zhang, C. H. Chang and S. Chen, “CMOS image sensor based physical unclonable function for smart phone security applications,” in Proc. 2014 International Symposium on Integrated Circuits (ISIC-2014), Marina Bay Sands, Singapore, pp. 392-395, 10-12 December 2014.
C135. W. Wei, L. Zhang and C. H. Chang, “A modular design of elliptic-curve point multiplication for resource constrained devices,” in Proc. 2014 International Symposium on Integrated Circuits (ISIC-2014), Marina Bay Sands, Singapore, pp. 596-599, 10-12 December 2014.
C134. V. V. Sergeichik, A. A. Ivaniuk and C. H. Chang, “Obfuscation and watermarking of FPGA designs based on constant value generators,” in Proc. 2014 International Symposium on Integrated Circuits (ISIC-2014), Marina Bay Sands, Singapore, pp. 608-611, 10-12 December 2014.
C133. L. Zhang and C. H. Chang, “Hardware trojan detection with linear regression based gate-level characterization,” in Proc. 2014 IEEE Asia Pacific Conf. on Circuits and Systems (APCCAS-2014), Okinawa, Japan, pp. 256-259, 17-20 November 2014.
C132. T. F. Tay and C. H. Chang, “New algorithm for signed integer comparison in four-moduli superset {2^n, 2^n-1, 2^n+1, 2^{n+1}-1},” in Proc. 2014 IEEE Asia Pacific Conf. on Circuits and Systems (APCCAS-2014), Okinawa, Japan, pp. 519-522, 17-20 November 2014.
C131. L. Zhang, Z. H. Kong, C. H. Chang, A. Cabrini and G. Torelli, “Leakage-resilience enhancement of memory-based physical unclonable function using phase change memory,” in Proc. 48th IEEE International Carnahan Conference on Security Techhnology (ICCST-2014), Rome, Italy, pp. 1-6, 13-16 October 2014.
C130. J. Chen and C. H. Chang, “Design of programmable FIR filters using canonical double based number representation,” in Proc. 2014 IEEE International Symposium on Circuits and Systems (ISCAS-2014), Melbourne, Australia, pp. 1183-1186, 1-5 June 2014.
C129. L. Zhang, X. Fong, C. H. Chang, Z. H. Kong and K. Roy, “Highly reliable physical unclonable function using spin-transfer torque MRAM,” in Proc. 2014 IEEE International Symposium on Circuits and Systems (ISCAS-2014), Melbourne, Australia, pp. 2169-2172, 1-5 June 2014.
C128. C. H. Chang and S. Kumar, “Area-efficient and fast sign detection for four-moduli set RNS {2^n-1, 2^n, 2^n+1, 2^(2n)+1},” in Proc. 2014 IEEE International Symposium on Circuits and Systems (ISCAS-2014), Melbourne, Australia, pp. 1540-1543, 1-5 June 2014.
C127. T. H. Tay and C. H. Chang, “A new agorithm for single residue digit error correction in redundant residue number system,” in Proc. 2014 IEEE International Symposium on Circuits and Systems (ISCAS-2014), Melbourne, Australia, pp. 1748-1751, 1-5 June 2014.
C126. L. Zhang, X. Fong, C. H. Chang, Z. H. Kong and K. Roy, “Feasibility study of emerging non-volatile memory based physical unclonable functions,” in Proc. 6th IEEE International Memory Workshop (IMW-2014), Taipei, Taiwan, pp. 135-138, 18-21 May 2014.  
C125. M. R. Meher, C. C. Jong and C. H. Chang, “A new approach of realizing high-speed DCT core using sign-digit up/down counters,” in Proc. 8th Intelligent Living Technology Conference (ILT 2013), National Chin-Yi University of Technology, Taichung, Taiwan, pp. 785-788, 7 June 2013 (Invited Paper).
C124. J. Y. S. Low and C. H. Chang, “A survey on scaling in residue number system,” in Proc. 8th Intelligent Living Technology Conference (ILT 2013), National Chin-Yi University of Technology, Taichung, Taiwan, pp. 789-794,7 June 2013 (Invited Paper).
C123. L. Zhang, Z. H. Kong and C. H. Chang, “PCKGen: a phase change memory based cryptographic key generator,” in Proc. 2013 IEEE International Symposium on Circuits and Systems (ISCAS-2013), Beijing, China, pp. 1444-1447, 19-23 May 2013.
C122. Y. Cao, C. H. Chang and S. Chen, “Cluster-based distributed active current timer for hardware trojan detection,” in Proc. 2013 IEEE International Symposium on Circuits and Systems (ISCAS-2013), Beijing, China, pp. 1010-1013, 19-23 May 2013.
C121. J. Y. S. Low, T. H. Tay and C. H. Chang, “A signed integer programmable power-of-two scaler for {2^n−1, 2^n, 2^n+1} RNS,” in Proc. 2013 IEEE International Symposium on Circuits and Systems (ISCAS-2013), Beijing, China, pp. 2211-2214, 19-23 May 2013.
C120. H. Qian and C. H. Chang, “Microchannel splitting and scaling for thermal balancing of liquid-cooled 3DIC,” in Proc. 2013 IEEE International Symposium on Circuits and Systems (ISCAS-2013), Beijing, China, pp. 801-804, 19-23 May 2013.
C119. H. Qian, H. Liang, C. H. Chang, W. Zhang and H. Yu, “Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects,” in Proc. 18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013), Yokohama, Japan, pp. 485-490, 22-23 January 2013 (one of 97 regular papers accepted out of 311 submitted papers, acceptance rate < 31.2%).
C118. A. Cui and C. H. Chang, “A post-processing scan-chain watermarking scheme for VLSI intellectual property protection,” in Proc. 2012 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS-2012), Kaohsiung, Taiwan, pp. 412-415, 2-5 December 2012.
C117. J. Y. S. Low, T. F. Tay and C. H. Chang, “A unified {2^n−1, 2^n, 2^n+1} RNS scaler with dual scaling constants,” in Proc. 2012 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS-2012), Kaohsiung, Taiwan, pp. 296-299, 2-5 December 2012.
C116. H. Tang, J. Y. L. Low, J. Y. S. Low, L. Siek, C. C. Jong and C. H. Chang, “A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion,” in Proc. 2012 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS-2012), pp. 272-275, Kaohsiung, Taiwan, 2-5 December 2012.
C115. L. Zhang and C. H. Chang, “State encoding watermarking for field authentication of sequential circuit intellectual property,” in Proc. 2012 IEEE International Symposium on Circuits and Systems (ISCAS-2012), Seoul, Korea, pp. 3013-3016, 20-23 May 2012.
C114. M. Kumm, P. Zipf, M. Faust and C. H. Chang, “Pipelined adder graph optimization for high speed multiple constant multiplication,” in Proc. 2012 IEEE International Symposium on Circuits and Systems (ISCAS-2012), Seoul, Korea, pp. 49-52, 20-23 May 2012.
C113. J. Y. L. Low, C. C. Jong, J. Y. S. Low, T. F. Tay and C. H. Chang, “A fast and compact circuit for integer square root computation based on Mitchell logarithmic method,” in Proc. 2012 IEEE International Symposium on Circuits and Systems (ISCAS-2012), Seoul, Korea, pp. 1235-1238, 20-23 May 2012.  
C112. F. Li, A. Basu, C. H. Chang and A. H. Cohen, “Dynamical systems: a tool for analysis and design of silicon half center oscillators,” in Proc. 2011 IEEE Biomedical Circuits & Systems Conference (BioCAS 2011), Diego, California, pp. 249-252, 10-12 November, 2011.
C111. M. Faust and C. H. Chang, “Low error bit width reduction for structural adders of FIR filters,” in Proc. 20th European Conference on Circuit Theory and Design (ECCTD 2011), Linköping, Sweden, pp. 713-716, 29-31 August 2011.
C110. J. Y. S. Low and C. H. Chang, “A new RNS scaler for {2^n–1, 2^n, 2^n+1},” in Proc. 2011 IEEE International Symposium on Circuits and Systems (ISCAS-2011), Rio de Janeiro, Brazil, pp. 1431-1434, 15-18 May 2011.
C109. R. Muralidharan and C. H. Chang, “A simple radix-4 Booth encoded modulo 2^n+1 multiplier,” in Proc. 2011 IEEE International Symposium on Circuits and Systems (ISCAS-2011), Rio de Janeiro, Brazil, pp. 1163-1166, 15-18 May 2011.
C108. M. Faust and C. H. Chang, “Bit-parallel multiple constant multiplication using Look-Up tables on FPGA,” in Proc. 2011 IEEE International Symposium on Circuits and Systems (ISCAS-2011), Rio de Janeiro, Brazil, pp. 657-660, 15-18 May 2011.
C107. A. Cui, C. H. Chang and L. Zhang, “A hybrid watermarking scheme for sequential functions,” in Proc. 2011 IEEE International Symposium on Circuits and Systems (ISCAS-2011), Rio de Janeiro, Brazil, pp. 2333-2336, 15-18 May 2011.
C106. H. Qian, X. Huang, H. Yu and C. H. Chang, “Real-time thermal management of 3D multi-core system with fine-grained cooling control,” in Proc. 2010 IEEE International 3D System Integration Conference, Munich, Germany, pp. 1-6, 16-18 November 2010.
C105. M. Faust, O. Gustafsson and C. H. Chang, “Reconfigurable multiple constant multiplication using minimum adder depth,” in Proc. 44th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, USA, 7-10 November 2010.
C104. F. Li, C. H. Chang and S. Liter, “A very low power 0.7 V subthreshold fully programmable Gaussian function generator” in Proc. 2nd IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia 2010), Shanghai, China, pp. 198-201, 22-24 September 2010 (Gold Leaf Certificate Award – top 10%).
C103. M. Faust and C. H. Chang, “Reduction of partial product matrix for high-speed single or multiple constant multiplication” in Proc. 2nd IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia 2010), Shanghai, China, pp. 416-420, 22-24 September 2010 (Silver Leaf Certificate Award – top 10-20%).
C102. B. Cao, Y. S. Low, C. H. Chang and T. Srikanthan, “Performance analysis of different special moduli sets for RNS-based inner product step processor,” in Proc. 2010 International Conference on Green Circuits and Systems (ICGCS-2010), Shanghai, China, pp. 236-241, 21-23 June, 2010 (Invited paper).
C101. M. R. Meher, C. C. Jong, C. H. Chang and J. Y. S. Low,“A novel counter-based low complexity inner-product architecture for high speed inputs,” in Proc. 2010 IEEE International Symposium on Circuits and Systems (ISCAS-2010), Paris, France, pp. 705-708, 30 May-2 June 2010
C100. M. Faust and C. H. Chang, “Minimal logic depth adder tree optimization for multiple constant multiplication,” in Proc. 2010 IEEE International Symposium on Circuits and Systems (ISCAS-2010), Paris, France, pp. 457-460, 30 May-2 June 2010.
C99. R. Muralidharan and C. H. Chang, “Fast hard multiple generators for radix-8 Booth encoded modulo 2^n-1 and modulo 2^n+1 multipliers,” in Proc. 2010 IEEE International Symposium on Circuits and Systems (ISCAS-2010), Paris, France, pp. 717-720, 30 May-2 June 2010.
C98. R. Muralidharan and C. H. Chang, “Hard multiple generator for higher radix modulo 2^n-1 multiplication,” in Proc. 2009 International Symposium on Integrated Circuits (ISIC-2009), Singapore, pp. 546-549, 14-16 December 2009.
C97. T. B. Juang, C. H. Chang and C. C. Wei, “Area-saving technique for low-error redundant binary fixed-width multiplier implementation,” in Proc. 2009 International Symposium on Integrated Circuits (ISIC-2009), pp. 550-553, Singapore, 14-16 December 2009.
C96. J. Chen, C. H. Chang and C. C. Jong, “Time-multiplexed data flow graph for the design of configurable multiplier block,” in Proc. International Symposium on Circuits and Systems (ISCAS-2009), Taipei, Taiwan, pp, 1145-1148, 24-27 May 2009.
C95. M. Faust and C. H. Chang, “Optimization of structural adders in fixed coefficient transposed direct form FIR filters,” in Proc. International Symposium on Circuits and Systems (ISCAS-2009), Taipei, Taiwan, pp. 2185-2188, 24-27 May 2009.
C94. F. Li, C. H. Chang and S. Liter, “A compact current mode neuron circuit with Gaussian taper learning capability,” in Proc. International Symposium on Circuits and Systems (ISCAS-2009), Taipei, Taiwan, pp. 2129-2132, 24-27 May 2009.
C93. J. Chen, C. H. Chang and H. Qian, “New power index model for switching power analysis from adder graph of FIR filter,” in Proc. International Symposium on Circuits and Systems (ISCAS-2009), Taipei, Taiwan, pp. 2197-2200, 24-27 May 2009.
C92. A. Cui and C. H. Chang, “An improved publicly detectable watermarking scheme based on scan chain ordering,” in Proc. International Symposium on Circuits and Systems (ISCAS-2009), Taipei, Taiwan, pp. 29-32, 24-27 May 2009.
C91. R. Muralidharan and C. H. Chang, “Fixed and variable multi-modulus squarer architectures for triple moduli base of RNS,” in Proc. International Symposium on Circuits and Systems (ISCAS-2009), Taipei, Taiwan, pp. 441-444, 24-27 May 2009.
C90. R. Muralidharan, C. H. Chang and C. C. Jong, “A low complexity modulo 2^n+1 squarer design,” in Proc. 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS-2008), Macao, China, pp. 1296-1299, 30 Nov.-3 December 2008.
C89. M. R. Meher, C. C. Jong and C. H. Chang, “High-speed and low-power serial accumulator for serial-parallel multiplier,” in Proc. 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS-2008), Macao, China, pp. 176-179, 30 Nov.-3 December 2008.
C88. A. Cui and C. H. Chang, “Intellectual property authentical by watermarking scan chain in design-for-testability flow,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2008), Seattle, USA, pp. 2645-2648,18-21 May 2008.
C87. R. K. Satzoda, R. Muralidharan and C. H. Chang, “Programmable LSB-first and MSB-first modular multiplier for ECC in GF(2^m),” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2008), Seattle, USA, pp. 808-811, 18-21 May 2008.
C86. R. K. Satzoda, H. N. Quang and C. H. Chang, “Programmable Montgomery modular multiplier for trinomonial reduction polynomials in GF(2^m),” in Proc. 2007 International Conference on Integrated Circuits (ISIC-2007), Singapore, pp. 224-227, 26-29 September 2007.
C85. A. Cui and C. H. Chang, “Watermarking for IP protection through template substitution at logic synthesis level,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2007), New Orleans, USA, pp. 3687-3690, 27-30 May 2007.
C84. S. Menon and C. H. Chang, “A reconfigurable multi-modulus modulo multiplier,” in Proc. 2006 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS-2006), Singapore, pp. 1168-1171, 4-7 December 2006.
C83. A. Cui and C. H. Chang, “Kernel extraction for watermarking combinational logic networks,” in Proc. 2006 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS-2006), Singapore, pp. 1023-1026, 4-7 December 2006.
C82. U. Meyer-Baese, J. Chen, C. H. Chang and A. G. Dempster, “A comparison of pipelined RAG-n and DA FPGA-based multiplierless filters,” in Proc. 2006 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS-2006), Singapore, pp. 1557-1560, 4-7 December 2006.
C81. J. Chen, C. H. Chang and A. P. Vinod, “Design of high-speed, low-power FIR filters with fine-grained cost metrics,” in Proc. 2006 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS-2006), Singapore, pp. 757-760, 4-7 December 2006.
C80. A. P. Vinod, C. H. Chang, P. K. Meher and A. Singla, “Low power FIR filter realization using minimal difference coefficients: Part I-Complexity Analysis,” in Proc. 2006 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS-2006), Singapore, pp. 1547-1550, 4-7 December 2006.
C79. A. P. Vinod, C. H. Chang, P. K. Meher and A. Singla,“Low power FIR filter realization using minimal difference coefficients: Part II-Algorithm,” in Proc. 2006 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS-2006), Singapore, pp. 1551-1554, 4-7 December 2006.
C78. R. K. Satzoda, C. H. Chang and C. C. Jong, “High Speed Systolic Montgomery Modular Multipliers for RSA Cryptosystems,” in Proc. 5th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems, (IMCAS-2006), Hangzhou, China, pp. 240-245, 16-18 April 2006 (Invited paper).
C77. Y. Shao and C. H. Chang, “A novel hybrid neuro-wavelet system for robust speech recognition,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2006), Kos, Greece, pp. 1852-1855, 21-24 May 21-24 2006.
C76. Y. Shao and C. H. Chang, “A Kalman filter based on wavelet filter-bank and psychoacoustic modeling for speech enhancement,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2006), Kos, Greece, pp. 121-124, 21-24 May 2006.
C75. Y. Shao and C. H. Chang, “A generalized perceptual time-frequency subtraction method for speech enhancement,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2006), Kos, Greece, pp. 2537-2540, 21-24 May 2006.
C74. F. Xu, C. H. Chang and C. C. Jong, “A new integrated approach to the design of low-complexity FIR filters,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2006), Kos, Greece, pp. 601-604, 21-24 May 2006.
C73. Y. He and C. H. Chang, “A low-power, high-speed RB-to-NB converter for fast redundant binary multiplier,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2006), Kos, Greece, pp. 2405-2408, 21-24 May 2006.
C72. C. H. Chang, J. Chen and A. P. Vinod, “Maximum likelihood disjunctive decomposition to reduced multirooted DAG for FIR filter design,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2006), Kos, Greece, pp. 613-616, 21-24 May 2006.
C71. R. K. Satzoda and C. H. Chang, “A fast kernel for unifying GF(p) and GF(2^m) montgomery multiplications in a scalable pipelined architecture,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2006), Kos, Greece, pp. 3378-3381, 21-24 May 2006.
C70. A. Cui and C. H. Chang, “Stego-signature at logic synthesis level for digital design IP protection,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2006), Kos, Greece, pp. 4611-4614, 21-24 May 2006.
C69. A. P. Vinod, C. H. Chang and A. Singla, “Improved differential coefficients-based low power FIR filters: Part I – Fundamentals,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2006), Kos, Greece, pp. 617-620, 21-24 May 2006.
C68. Y. He, C. H. Chang, J. Gu and H. A. H. Fahmy, “A novel covalent redundant binary Booth encoder,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2005), Kobe, Japan, pp. 69-72, 23-26 May 2005.
C67. Y. He, C. H. Chang and J. Gu, “An area efficient 64-bit square root carry-select adder for low power applications,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2005), Kobe, Japan, pp. 4082-4085, 23-26 May 2005.
C66. B. Cao, T. Srikanthan and C. H. Chang, “A new design method to modulo 2^n-1 squaring,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2005), Kobe, Japan, pp. 664-667, 23-26 May 2005.
C65. B. Cao, C. H. Chang and T. Srikanthan, “A new formulation of fast diminished-one multioperand modulo 2^n+1 adder,” in Proc. International Symposium on Circuits and Systems (ISCAS-2005), Kobe, Japan, pp. 656- 659, 23-26 May 2005.
C64. C. H. Chang, R. K. Satzoda and S. Sekar, “A novel multiplexer based truncated array multiplier,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2005), Kobe, Japan, pp. 85-88, 23-26 May 2005.
C63. Y. Shao and C. H. Chang, “Wavelet transform to hybrid support vector machine and hidden Markov model for speech recognition,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2005), Kobe, Japan, pp. 3833-3836, 23-26 May 2005.
C62. Y. Shao and C. H. Chang, “A versatile speech enhancement system based on perceptual wavelet denoising,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2005), Kobe, Japan, pp. 864-867, 23-26 May 2005.
C61. C. H. Chang, S. Menon, B. Cao and T. Srikanthan, “A configurable dual moduli multi-operand modulo adder,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2005), Kobe, Japan, pp. 1630-1633, 23-26 May 2005.
C60. F. Xu, C. H. Chang and C. C. Jong, “I2CRA: Contention resolution algorithm for intra- and inter-coefficient common subexpression elimination,” Special Session on Low Complexity Digital Filter Design Techniques and Their Applications, in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2005), Kobe, Japan, pp. 1823-1826, 23-26 May 2005.
C59. S. Udit, F. Xu, C. H. Chang, C. C. Jong and K. S. Yeo, “sys-FIR: A compiler for evaluating VLSI performance metrics of reduced adder cost FIR filters,” in Proc. IEEE International Symposium on Low-power and High-speed Chips (Cool Chips VIII), Yokohama Joho Bunka Centre, Yokohama, Japan, pp.339-346, April 20-22, 2005.
C58. X. Deng, P. Xu, and C. H. Chang, “Self organizing topological tree for skin color detection,” in Proc. IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS-2004), Tainan, Taiwan, pp. 1097-1100, 6-9 December 2004.
C57. F. Xu, J. Chen, C. H. Chang and C. C. Jong, “A modified reduced adder graph algorithm for multiplier block minimization in digital filters,” in Proc. IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS-2004), Tainan, Taiwan, pp. 705-708, 6-9 December 2004.
C56. C. H. Chang, Y. He and J. Gu, “An alternative scheme for redundant binary multiplier,” in Proc. IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS-2004), Tainan, Taiwan, pp. 33-36, 6-9 December 2004.
C55. B. Cao, T. Srikanthan and C. H. Chang, “Design of residue-to-binary converter for a new 5-moduli superset residue number system,” in Proc. 37th IEEE International Symposium on Circuits and Systems (ISCAS-2004), Vancouver, Canada, Vol. II, pp. 841-844, 23-26 May 2004.
C54. F. Xu, C. H. Chang and C. C. Jong, “A new contention resolution algorithm for the design of minimal logic depth multiplierless filters,” in Proc. 37th IEEE International Symposium on Circuits and Systems (ISCAS-2004), Vancouver, Canada, Vol III, pp.481-484, 23-26 May 2004.
C53. F. Xu, C. H. Chang and C. C. Jong, “HWP: a new insight into canonical signed digit,” in Proc. 37th IEEE International Symposium on Circuits and Systems (ISCAS-2004), Vancouver, Canada, Vol. V, pp. 201-204, 23-26 May 2004.
C52. C. H. Chang and P. Xu, “Frequency sensitive self-organzing maps and its application in color quantization,” in Proc. 37th IEEE International Symposium on Circuits and Systems (ISCAS-2004), Vancouver, Canada, Vol. V, pp804-807, 23-26 May 2004.
C51. P. Xu and C. H. Chang, “Self-organizing topological tree,” in Proc. 37th IEEE Int. Symp. on Circuits and Systems (ISCAS-2004), Vancouver, Canada, Vol. V, pp. 732-735, 23-26 May 2004.
C50. F. Xu, C. H. Chang and C. C. Jong, “Efficient algorithm for common subexpression elimination in digital filter design,” in Proc. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP-2004), Montreal, Canada, Vol. V, pp. 137-140, 17-21 May 2004.
C49. J. Gu, C. H. Chang and K. S. Yeo, “An area and energy efficient IP core for scalar product computation,” in Proc. IEEE International Symposium on Low-power and High-speed Chips, Cool Chips VII, Yokohama, Japan, Vol. 1, pp.219-226, 14-16 April 2004.
C48. X. Deng, C. H. Chang and E. Brandle, “A new method for eye extraction from facial image,” in Proc. 2nd IEEE International Workshop on Electronic Design, Test and Applications (DELTA-2004), Perth, Australia, pp. 29-34, January 2004.
C47. Z. Ye and C. H. Chang, “Local search method for FIR filter coefficients synthesis,” in Proc. 2nd IEEE International Workshop on Electronic Design, Test and Applications (DELTA-2004), Perth, Australia, pp. 255-260, January 2004.
C46. Z. Ye, R. K. Satzoda, U. Sharma, N. Nazimudeen and C. H. Chang, “Performance evaluation of direct form FIR filter with merged arithmetic architecture,” in Proc. 2nd IEEE International Workshop on Electronic Design, Test and Applications (DELTA-2004), Perth, Australia, pp. 407-409, January 2004.
C45. C. H. Chang, M. Zhang and J. Gu, “A novel low power low voltage full adder cell,” in Proc. 3rd IEEE/EURASIP International Symposium on Image and Signal Processing and Analysis (ISPA-2003), Rome, Italy, pp. 454-458, September 2003.
C44. B. Cao, C. H. Chang and T. Srikanthan, “Adder based residue to binary converters for a new balanced 4-moduli set,” in Proc. 3rd IEEE/EURASIP International Symposium on Image and Signal Processing and Analysis (ISPA-2003), Rome, Italy, pp. 820-825, September 2003.
C43. Z. Ye and C. H. Chang, “A hybrid CSA tree for merged arithmetic architecture of FIR filter,” in Proc. 3rd IEEE/EURASIP International Symposium on Image and Signal Processing and Analysis (ISPA-2003), Rome, Italy, pp. 449-453, September 2003.
C42. B. Cao, T. Srikanthan and C. H. Chang, “Design of a high speed reverse converter for a new 4-moduli set residue number system,” in Proc. 36th IEEE International Symposium on Circuits and Systems (ISCAS-2003), Bangkok, Thailand, Vol. IV, pp. 520-523, May 2003.
C41. B. Cao, C. H. Chang and T. Srikanthan, “New efficient residue-to-binary converters for 4-moduli set {2^n-1, 2^n, 2^n+1, 2^(n+1)-1},” in Proc. 36th IEEE International Symposium on Circuits and Systems (ISCAS-2003), Bangkok, Thailand, Vol. IV, pp. 536-539, May 2003.
C40. M. Zhang, J. Gu and C. H. Chang, “A novel hybrid pass logic with static CMOS output drive full-adder cell,” in Proc. 36th IEEE International Symposium on Circuits and Systems (ISCAS-2003), Bangkok, Thailand, Vol. V, pp. 317-320, May 2003.
C39. J. Gu and C. H. Chang, “Ultra low voltage, low power 4-2 compressor for high speed multiplications,” in Proc. 36th IEEE International Symposium on Circuits and Systems (ISCAS-2003), Bangkok, Thailand, Vol. V, pp. 321-324, May 2003.
C38. M. Shibu, C. H. Chang and R. Xiao, “FPGA implementation of a frequency adaptive learning SOFM for digital color still imaging,” in Proc. 36th IEEE International Symposium on Circuits and Systems (ISCAS-2003), Bangkok, Thailand, Vol. II, pp. 452-455, May 2003.
C37. C. H. Chang, R. Xiao and T. Srikanthan, “An adaptive initialization technique for color quantization by self organizing feature map,” in Proc. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP-2003), Hong Kong, Vol III, pp. 477-480, April 2003.
C36. J. Gu and C. H. Chang, “Low voltage, low power (5:2) compressor cell for fast arithmetic circuits,” in Proc. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP-2003), Hong Kong, Vol. II, pp. 661-664, April 2003.
C35. X. Yang and C. H. Chang, “A feasibility study of embedded Linux for the software defined radio,” in Proc. 2003 IEEE Sarnoff Symposium on Advances in Wired and Wireless Communications, New Jersey, USA, pp. 131-134, March 2003.
C34. X. Yang and C. H. Chang, “A practical approach for automatic recognition and identification of digital modulations,” in Proc. 2003 IEEE Sarnoff Symposium on Advances in Wired and Wireless Communications, New Jersey, USA, pp. 135-138, March 2003.
C33. C. H. Chang, R. Xiao and T. Srikanthan, “A MSB-biased self-organizing feature map for still color image compression,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS-2002), Bali, Indonesia, Vol. 2, pp. 85-88, October 2002.
C32. C. H. Chang, Z. Ye and M. Zhang, “Fuzzy-ART based digital watermarking scheme,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS-2002), vol. 1, pp. 423-426, Bali, Indonesia, October 2002.
C31. H. Tian, S. K. Lam, T. Srikanthan and C. H. Chang, “An efficient architecture for adaptive progressive thresholding,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS-2002), Bali, Indonesia, Vol. 1, pp. 513-516, October 2002.
C30. A. Ehrensperger, C. H. Chang, J. G. Ma, F. Schnyder and C. Haller, “Fixed-point DSP implementation of mixed demodulator for digital FM radio receiver,” in Proc. IEEE International Symposium on Consumer Electronics (ISCE-2002), Erfurt, Germany, pp. IF77-82, September 2002.
C29. X. Yang and C. H. Chang, “Bluetooth enabled embedded Linux,” in Proc. 9th International Linux Systems Technology Conf. (Linux-Kongress 2002), Cologne, Germany, pp. 14-29, September 2002.
C28. C. H. Chang, M. Zhang and Z. Ye, “A content-dependent robust and fragile watermarking scheme,” in Proc. 2nd IASTED International Conference on Visualization, Imaging and Image Processing (VIIP-2002), Malaga, Spain, pp. 201-206, September 2002.
C27. R. Xiao, C. H. Chang and T. Srikanthan, “A new localized learning scheme for self-organizing feature maps,” in Proc. 2nd IASTED International Conference on Visualization, Imaging and Image Processing (VIIP-2002), Malaga, Spain, pp. 261-264, September 2002.
C26. J. Gu, C. H. Chang and K. S. Yeo, “An interconnect optimized floorplanning of a scalar product macrocell,” in Proc. 35th IEEE International Symposium on Circuits and Systems (ISCAS-2002), Scottsdale, Arizona, USA., Vol. I, pp. 465-468, May 2002.
C25. R. Xiao, C. H. Chang and T. Srikanthan, “On the initialization and training methods for Kohonen self-organizing feature maps in color image quantization,” in Proc. 1st International Workshop on Electronic Design, Test and Applications (DELTA-2002), Christchurch, New Zealand, pp. 321-325, January 2002.
C24. C. H. Chang and B. J. Falkowksi, “Graph based analysis and computation of Reed-Muller weight vectors,” in Proc. 9th International Symposium on Integrated Circuits, Devices and Systems (ISIC-2001), Singapore, pp. 484-487, September 2001.
C23. D. J. Ho, C. H. Chang, H. Z. Peh and R. Meyyappan, “Architecture of a hardware module for GSM vocoder,” in Proc. 9th International Symposium on Integrated Circuits, Devices and Systems (ISIC-2001), Singapore, pp. 362- 365, September 2001.
C22. C. H. Chang and B. J. Falkowksi, “Reed-Muller transform based Boolean matching filters,” in Proc. 15th European Conference on Circuit Theory and Design (ECCTD-2001), Espoo, Finland, pp. 285-288, August 2001.
C21. C. H. Chang and B. J. Falkowski, "Reed-Muller weight and literal vectors for NPN classification," in Proc. 32nd IEEE International Symposium on Circuits and Systems (ISCAS-1999), Orlando, Florida, USA, Vol. I, pp. 379-382, Jul 1999.
C20. B. J. Falkowski and C. H. Chang, "Optimization of partially-mixed polarity Reed-Muller expansions," in Proc. 32nd IEEE International Symposium on Circuits and Systems (ISCAS-1999), Orlando, Florida, USA, Vol I, pp. 383-386, Jul 1999.
C19. C. H. Chang and B. J. Falkowski, "Generation of quasi-optimal FBDDs through paired Haar spectra," in Proc. 31st IEEE International Symposium on Circuits and Systems (ISCAS-1998), Monterey, California, USA,Vol. VI, pp. 167-170, June 1998.
C18. B. J. Falkowski and C. H. Chang, "Calculation of paired Haar spectra for systems of incompletely specified Boolean functions," in Proc. 31st IEEE International Symposium on Circuits and Systems (ISCAS-1998), Monterey, California, USA, Vol. VI, pp. 171-174, June 1998.
C17. C. H. Chang and B. J. Falkowski, "In-place transformation of generalized and complex spectra through algebraic decision diagrams," in Proc. 1st IEEE International Conference on Information, Communications and Signal Processing (ISICS-1997), Singapore, Vol. 1, pp. 256-260, September 1997.
C16. B. J. Falkowski and C. H. Chang, "Properties and applications of paired Haar transform," in Proc. 1st International Conference on Information, Communications and Signal Processing (ISICS-1997), Singapore, Vol. 1, pp. 48-51, September 1997.
C15. C. H. Chang and B. J. Falkowski, "Boolean matching for generic FPGAs," in Proc. 30th IEEE International Symposium on Circuits and Systems (ISCAS-1997), Hong Kong, Vol.3, pp. 1700-1703, June 1997.
C14. B. J. Falkowski and C. H. Chang, "Calculation of arithmetic spectra from free binary decision diagrams," in Proc. 30th IEEE International Symposium on Circuits and Systems (ISCAS-1997), Hong Kong, Vol 3, pp. 1764-1767, June 1997.
C13. B. J. Falkowski and C. H. Chang, "Minimization of partially-mixed-polarity Reed-Muller expansions for multiple output incompletely specified Boolean functions," in Proc. 6th Workshop on Post Binary Ultra-Large Scale Integration (WPBULSI-1997), Antigonish, Nova Scotia, Canada, pp. 45-46, May 1997.
C12. C. H. Chang and B. J. Falkowski, "Operations on Boolean functions and variables in spectral domain of arithmetic transform," in Proc. 29th IEEE International Symposium Circuits and Systems (ISCAS-1996), Atlanta, Georgia, USA, Vol. 4, pp. 400-403, May 1996.
C11. C. H. Chang and B. J. Falkowski, "Flexible optimization of fixed polarity Reed-Muller expansions for multiple output completely and incompletely specified Boolean functions," in Proc. IEEE/IEICE Asia and South Pacific Design Automation Conference (ASP-DAC 1995), Makuhari, Chiba, Japan, pp. 335-340, August 1995.
C10. B. J. Falkowski and C. H. Chang, "Fast generalized arithmetic and adding transforms," in Proc. 8th IFIP WG10.5 International Conference on Very Large Scale Integration (VLSI-1995), Makuhari, Chiba, Japan, pp. 723-728, August 1995. (Best paper award candidate).
C9. B. J. Falkowski and C. H. Chang, "Generation of multi-polarity arithmetic transform from reduced representation of Boolean functions," in Proc. 28th IEEE International Symposium on Circuits and Systems (ISCAS-1995), Seattle, Washington, USA, pp. 2168-2171, May 1995.
C8. B. J. Falkowski and C. H. Chang "Efficient algorithms for the calculation of Walsh spectrum from BDD and synthesis of BDD from Walsh spectrum for incompletely specified Boolean functions", in Proc. 37th IEEE Midwest Symposium on Circuits and Systems (MWSCAS-1994), Lafayette, Louisiana, USA, pp. 393-396, August 1994.
C7. B. J. Falkowski and C. H. Chang, "Efficient algorithms for the calculation of arithmetic spectrum from OBDD and synthesis of OBDD from arithmetic spectrum for incompletely specified Boolean functions", in Proc. 27th IEEE International Symposium on Circuits and Systems (ISCAS-1994), London, United Kingdom, vol. 1, pp. 197-200, May 1994.
C6. B. J. Falkowski and C. H. Chang, "Efficient algorithms for forward and inverse transformations between Haar spectrum and binary decision diagram", in Proc. 13th IEEE International Phoenix Conference on Computers and Communications (IPCCC-1994), Phoenix, Arizona, USA, pp. 497-503, April. 1994.
C5. B. J. Falkowski and C. H. Chang, "Generation of fixed polarity Reed-Muller expansions from subset of Walsh spectral coefficients for completely specified Boolean functions," in Proc. 5th International Workshop on Spectral Techniques (IWST-1994), Beijing, China, pp. 214-219, March 1994.
C4. B. J. Falkowski and C. H. Chang, "A novel paired Haar based transform: algorithms and interpretations in Boolean domain," in Proc. 36th IEEE Midwest Symposium on Circuits and Systems (MWSCAS-1993), Detroit, Michigan, USA, pp. 1101-1104, August 1993.
C3. B. J. Falkowski, I. Schaefer and C. H. Chang, "An efficient computer algorithm for the calculation of disjoint cubes representation of Boolean functions", in Proc. 36th IEEE Midwest Symposium on Circuits and Systems (MWSCAS-1993), Detroit, Michigan, USA, pp. 1308-1311, August 1993.
C2. M. A. Do, C. H. Chang and J. T. Ong, "Implementation of randomised time division multiplexing technique for automatic vehicle identification," in Proc. of the International Conference on Information Engineering (ICIE-1991), Singapore, pp. 740-749 , December 1991.
C1. M. A. Do, J. T. Ong, C. H. Chang, T. H. Ooi, and D. Mital, "Automatic vehicle identification on busy multi-lane city road," in Proc. of Vehicle Navigation & Information Systems (VNIS-1991), Dearborn, Michigon, USA, pp. 989-997, 1991.

Papers in Local Journals and Technical Reports:

LJ5. X. Deng, P. Xu and C. H. Chang, "Self organizing topological tree for scheme color detection," EEE Research Bulletin, NTU, Singapore, January 2005.
LJ4. Z. Ye, N. Nazimudeen and C. H. Chang, "Design of FIR filters with merged arithmetic architecture and delay-profile driven CPA," EEE Research Bulletin, NTU, Singapore, pp. 28-29, January 2004.
LJ3. M. A. Do, K. S. Yeo, J. G. Ma, Y. P. Zhang, P. K. Chan, C. H. Chang and K. Y. See, "Software radio system-on-chip," EEE Research Bulletin, NTU, Singapore, pp. 2-5, January 2002.
LJ2. J. Gu and C. H. Chang, "Multiplier based on redundant number representation in Booth encoded format," EEE Research Bulletin, NTU, Singapore, pp. 20-21, January 2002.
LJ1. B. J. Falkowski and C. H. Chang, “Fast Generalized Arithmetic Transform,” Electrical and Electronic Engineering Research, ISSN 0218-2602, pp. 6-7, January 1997.

Papers in Local Conferences:

LC9. J. Chen and C. H. Chang, “Design automation and optimization of FIR filters,” UK-Singapore Partners in Science – Microelectronics Embedded Systems Workshop (MES-2007), Singapore, 23-24 January 2007.
LC8. A. Cui and C. H. Chang, “Research in digital watermarking for IP protection,” UK-Singapore Partners in Science – Microelectronics Embedded Systems Workshop (MES-2007), Singapore, 23-24 January 2007.
LC7. R. K. Satzoda, C. H. Chang and T. Srikanthan, “Monte Carlo Statistical Analysis for Power Simulation in Synopsys Design Compiler,” Synopsys Users’ Group Conference, Singapore, Online publication, http://www.snug-universal.org/papers/papers.htm, Jun. 2006
LC6. S. Udit and C. H. Chang, "Modelling and simulation of fast multiplierless 2-D DCT architecture based on lifting scheme," Proceedings of the National Undergraduate Research Opportunity Program Congress (NUROP 2003), Singapore, September 2003.
LC5. N. Naveen and C. H. Chang, "Synthesis of hardware efficient FIR filter coefficients," Proceedings of the National Undergraduate Research Opportunity Program Congress (NUROP 2003), Singapore, September 2003.
LC3. X. Deng and C. H. Chang, "A review of potential image processing techniques for eyes tracking," Proceedings of the National Undergraduate Research Opportunity Program Congress (NUROP 2002), Singapore, September 2002.
LC2. B. R. S. Putra and C. H. Chang, "Feasibility study of hybrid GMSK and pi/4 DQPSK receiver architecture," Proceedings of the National Undergraduate Research Opportunity Program Congress (NUROP 2002), Singapore, September 2002
LC1. S. M. Lee, F. L. Leong, S. Y. Tan, C. H. Chang and Y. Lian, “Static timing analysis: a systematic approach to stamp modeling of complex blocks,” Synopsys User Group Conference (SNUG 2001), Singapore, 1 June 2001.

Graduate Students

1. Ms. Rui XIAO
Adaptive color quantization using self-organizing feature maps
MEng. degree conferred in 2003
Design Manager, Consumer Electronics, STMicroelectronics Pte. Ltd., Edinburgh, United Kingdom
2. Dr. Jiangmin GU
Low-voltage, low-power CMOS arithmetic circuits for energy efficient VLSI applications
PhD degree conferred in June 2005
Principle Engineer, Suzhou T-Create Co.
3. Ms. Zhi YE
Optimization of FIR filters with CSD coefficients
MEng. degree conferred in December 2004
Senior Engineer, R&D Engineering, Seagate Technology International.
4. Ms. Mingyan ZHANG
Low power, low voltage adder cells for digital multiplier
MEng. degree conferred in October 2004
Manager, Product Yield Analysis, Tech Seminconductor Pte. Ltd.
5. Dr. Pengfei XU
New self-organizing algorithms for topological maps
PhD degree conferred in January 2007
Lecturer, Department of Electronics, Beijing Normal University.
6. Dr. Yajuan HE
Design and analysis of redundant binary Booth multipliers
PhD degree conferred in June 2008
Associate Professor, University of Electronic Science and Technology of China.
7. Ms. Xiaoyun DENG
Efficient techniques for face and eye detection
MEng. degree conferred in October 2005
Project Lead, STMicroelectronics Pte. Ltd.
8. Mr. Xiaoyong YANG Marcus
Modeling, packaging and recognition of radio etiquettes for cognitive radio
MEng. degree conferred in June 2005
Key Account/Marketing Manager, Imaging Division, STMicroelectronic Ltd. United Kingdom.
9. Mr. Shibu MENON
Modulo adders, multipliers and shared-moduli architectures for moduli of type {2^n-1, 2^n, 2^n +1}
MEng. degree conferred in December 2007
DFT Manager, Intel Mobile Communications.
10. Dr. Fei XU
Algorithms for synthesis and optimization of multiplierless FIR filters
PhD thesis conferred in June 2007
Senior Test Software Engineer, Xilinx Asia Pacific Pte. Ltd.
11. Dr. Bin CAO
VLSI efficient architectures for triple moduli based RNS computations
PhD degree conferred in June 2006
Senior Research Fellow, Luminous, Nanyang Technological University.
12. Dr. Yu SHAO
Robust speech enhancement algorithms based on wavelet filterbank modeling of human auditory system
PhD degree conferred in March 2009
Manager and Principal Geophysicist, Seismic Imaging and Interpretation, Statoil ASA.
13. Dr. Aijiao CUI
Constraint-based watermarking techniques for VLSI intellectual property protection
PhD degree conferred in December 2009
Assistant Professor, Harbin Institute of Technology Shenzhen Graduate School, Shenzhen, China
14. Dr. Jiajia CHEN
New design methodologies for low complexity FIR filters and reconfigurable constant multipliers
PhD degree conferred in September 2010
Lecturer and Track Lead of Computer Engineering Track, Pillar of Engineering Product Development, Singapore University of Technology and Design (SUTD).
15. Dr. Ravi Kumar SATZODA
Fast finite field multipliers for public key cryptosystems
MEng. degree conferred in December 2007
Research Fellow, University of California, San Diego, USA.
16. Mr. Udit SHARMA
An integrated platform for design and verification of FIR filters
MEng. thesis degree conferred in November 2007
Manager, Global Management Team of Samsung Electronics, Korea.
17. Dr. Ramya MURALIDHARAN
Novel modulo multipliers for moduli 2^n-1, 2^n and 2^n+1
PhD degree conferred in October 2012.
Hardware Systems Engineer, Adeptence LLC, USA.
18. Dr. Manas Ranjan MEHER
New architectures of multipliers and inner product processors for high-speed on-chip serial-link bus
PhD. degree conferred May 2013
IC Design and Implementation Engineer, Infineon Technologies Asia Pacific Pte. Ltd.
19. Dr. Fei LI
Non-linear analog circuits for self-organizing neuron and central pattern generator
PhD. degree conferred in May 2013
Research Scientist, Data Storage Institute, Agency for Science, Technology and Research.
20. Dr. Mathias FAUST
Design methodologies for complexity reduction of FIR filters
PhD. thesis approved in September 2014
Head of IT, Gruner AG, Switzerland.
21. Dr. Hanhua QIAN
Thermal management of microfluidic cooled 3D integrated circuits
PhD. degree conferred in June 2014.
Research Scientist, Institute of High Performance Computing (IHPC), Agency for Science, Technology and Research (A*STAR).
22. Dr. Yung Shern LOW Jeremy
VLSI efficient RNS scalers and arbitrary modulus residue generators
PhD degree conferred in May 2014
Staff II Design Engineer, Broadcom Singapore.
23. Dr. Li ZHANG
Integrity protection and authentication of integrated circuit intellectual property cores
PhD. degree conferred in May 2015
Hardware Security Evaluator, UL-Transaction Security, Singapore.
24. Dr. Yuan CAO
Design of security primitives for trustworthy integrated circuits. PhD (Co-advisor), Degree conferred in January 2016.
Development Engineer, Advantest (Singapore) Pte. Ltd.
25. Dr. Thian Fatt TAY
New algorithms and architectures for VLSI efficient RNS computations. PhD. Degree conferred in June 2016
Engineer, Broadcom Singapore.
26. Dr. Le ZHANG
Emerging non-volatile memory based physical unclonable functions. PhD (Co-advisor).Degree conferred in May 2016.
Data Scientist, Microsoft Singapore
27. Mr. Sachin KUMAR
New algorithms for hardware-efficient implementation of sign detection and magnitude comparison in residue number systems. PhD thesis submitted January 2017.
28. Mr. Siarhei ZALIVAKA
Active metering scheme for digital rights management of integrated circuit IP cores. PhD.
29. Mr. HO Truong Phu Truan
Hardware-efficient homomorphic encryption for privacy-preserving authentication. PhD.
30. Ms. Yue ZHENG
Physical unclonable function for device fingerprinting and secret key Generation. PhD.
31. Mr. Chaoqun LIU
Design of a SRAM-based physical unclonable function system. MEng., supported by MediaTek
31. Mr. Yufei ZHANG
Hardware-efficient fault-tolerant computations by redundant residue representation. MEng., supported by Silicon Lab
32. Ms. Si WANG
Machine learning security: attacks and defenses, PhD.
33. Mr. Thwin MYINT
Design and implementation of MiniDisc recorder, MSc. (Consumer Electronics) degree conferred in 2001.
34. Mr. Chiang Poo TAN
Frequency adaptive learning SOFM for grayscale image compression, MSc (Consumer Electronics) degree conferred in 2003.
35. Ms. Linna MU
Performance evaluation of modulo adders and multipliers, MSc. (IC Design) degree conferred in 2005.
36. Mr. Sing Yu SU
A radix-16 54x54-bit redundant binary multiplier, MSc. (IC Design) degree conferred in 2006.
37. Mr. Boppu SRINIVAS
Advanced on chip variation modeling (AOCVM) analysis using Primetime, NTU-TUM MSc (IC Design) degree conferred in 2009.
38. Ms. Pratyaksha Navalkar Ravindra
Verification of single wire protocol’s macrocell, NTU-TUM MSc (IC Design) degree conferred in 2010.
39. Mr. Yao Liang CHUA, Ronald
Design and ASIC implementation of a residue number system scaler for moduli set {2n-1, 2n, 2n+1}. NTU-TUM MSc (IC Design) degree conferred in 2011.
40. Ms. Zhe DING
Development of universal verification methodology verification for serial peripheral interface macrocell. NTU-TUM MSc (IC Design) degree conferred in 2011 (Project with STMicroelectronics).
41. Mr. Mingtao LIU
Firmware design for LED lighting remote control. NTU-TUM MSc (IC Design) degree conferred in 2011 (Project with Infineon Technologies).
42. Mr. Anant Raj GUPTA
Next generation System-on-Chip interconnect concepts and implementation. NTU-TUM MSc (IC Design), degree conferred in 2012 (Project with Lantiq Singapore Pte. Ltd.).
43. Mr. Ji ZHOU
Standalone spread spectrum clock generator for master clock EMI reduction. NTU-TUM (IC Design), degree conferred in 2012 (Project with Infineon Technologies Asia Pacific Pte. Ltd.).
44. Mr. Sumeet SHRESTHA
Modeling and verification of central analog block and ambient light sensing for an image sensor. NTU-TUM (IC Design), degree conferred in 2013 (Project with STMicroelectronics)
45. Mr. Kye Howe WONG
System architecture modeling of gigabit Ethernet transceiver and implementation of digital signal processing modules. NTU-TUM MSc (IC Design), degree conferred in 2013 (Project with Lantiq Asia Pacific, Singapore).
46. MS. Hariharan KRISHNAMURTHY
Characterization of FPGA-simultaneous switching noise determination. NTU-TUM MSc (IC Design), degree conferred in 2014 (Project with Xilinx Asia Pacific Pte. Ltd., Singapore).
47. Mr. Srinivas DEEPAK
Area and power optimization of contactless interface unit blocks in smart cards for high speed near-field communications. NTU-TUM MSc (IC Design), degree conferred in 2014 (Project with NXP Research Asia Lab., Singapore).